/[dynamips]/trunk/dev_c3745.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.7-RC1/dev_c3745.h revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC upstream/dynamips-0.2.7-RC2/dev_c3745.h revision 8 by dpavlin, Sat Oct 6 16:24:54 2007 UTC
# Line 14  Line 14 
14  #include "net.h"  #include "net.h"
15  #include "device.h"  #include "device.h"
16  #include "pci_dev.h"  #include "pci_dev.h"
17  #include "nmc93c46.h"  #include "nmc93cX6.h"
18  #include "net_io.h"  #include "net_io.h"
19  #include "vm.h"  #include "vm.h"
20    
# Line 29  Line 29 
29  #define C3745_DEFAULT_DISK1_SIZE   0  #define C3745_DEFAULT_DISK1_SIZE   0
30  #define C3745_DEFAULT_IOMEM_SIZE   5   /* Percents! */  #define C3745_DEFAULT_IOMEM_SIZE   5   /* Percents! */
31    
32  /* 3745 characteritics: 2 NM, 3 WIC, 2 AIM */  /* 3745 characteritics: 4 NM, 3 WIC, 2 AIM */
33  #define C3745_MAX_NM_BAYS  5  #define C3745_MAX_NM_BAYS  5
34    
35  /* C3745 DUART Interrupt */  /* C3745 DUART Interrupt */
# Line 44  Line 44 
44  /* C3745 External Interrupt */  /* C3745 External Interrupt */
45  #define C3745_EXT_IRQ    6  #define C3745_EXT_IRQ    6
46    
47    /* Network IRQ */
48    #define C3745_NETIO_IRQ_BASE       32
49    #define C3745_NETIO_IRQ_PORT_BITS  2
50    #define C3745_NETIO_IRQ_PORT_MASK  ((1 << C3745_NETIO_IRQ_PORT_BITS) - 1)
51    #define C3745_NETIO_IRQ_PER_SLOT   (1 << C3745_NETIO_IRQ_PORT_BITS)
52    #define C3745_NETIO_IRQ_END        \
53        (C3745_NETIO_IRQ_BASE + (C3745_MAX_NM_BAYS * C3745_NETIO_IRQ_PER_SLOT) - 1)
54    
55  /* C3745 common device addresses */  /* C3745 common device addresses */
56  #define C3745_GT96K_ADDR      0x24000000ULL  #define C3745_GT96K_ADDR      0x24000000ULL
57  #define C3745_IOFPGA_ADDR     0x1fa00000ULL  #define C3745_IOFPGA_ADDR     0x1fa00000ULL
# Line 127  struct c3745_router { Line 135  struct c3745_router {
135     /* IO memory size to be passed to Smart Init */     /* IO memory size to be passed to Smart Init */
136     u_int nm_iomem_size;     u_int nm_iomem_size;
137    
138       /* I/O FPGA */
139       struct c3745_iofpga_data *iofpga_data;
140    
141     /* Chassis information */     /* Chassis information */
142     struct c3745_nm_bay nm_bay[C3745_MAX_NM_BAYS];     struct c3745_nm_bay nm_bay[C3745_MAX_NM_BAYS];
143     m_uint8_t oir_status;     m_uint8_t oir_status;
# Line 136  struct c3745_router { Line 147  struct c3745_router {
147      * It can be modified to change the chassis MAC address.      * It can be modified to change the chassis MAC address.
148      */      */
149     struct cisco_eeprom sys_eeprom[3];     struct cisco_eeprom sys_eeprom[3];
150     struct nmc93c46_group sys_eeprom_group;     struct nmc93cX6_group sys_eeprom_group;
151    
152     /* Network Module EEPROMs */     /* Network Module EEPROMs */
153     struct nmc93c46_group nm_eeprom_group[4];     struct nmc93cX6_group nm_eeprom_group[4];
154  };  };
155    
156  /* Create a new router instance */  /* Create a new router instance */
# Line 157  void c3745_save_config(c3745_t *router,F Line 168  void c3745_save_config(c3745_t *router,F
168  /* Save configurations of all C3745 instances */  /* Save configurations of all C3745 instances */
169  void c3745_save_config_all(FILE *fd);  void c3745_save_config_all(FILE *fd);
170    
171    /* Get network IRQ for specified slot/port */
172    u_int c3745_net_irq_for_slot_port(u_int slot,u_int port);
173    
174  /* Set NM EEPROM definition */  /* Set NM EEPROM definition */
175  int c3745_nm_set_eeprom(c3745_t *router,u_int nm_bay,  int c3745_nm_set_eeprom(c3745_t *router,u_int nm_bay,
176                          const struct cisco_eeprom *eeprom);                          const struct cisco_eeprom *eeprom);

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