dynamips/trunk/dev_c3745.h

/*
 * Cisco 3745 simulation platform.
 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
 *
 * Generic Cisco 3745 routines and definitions (EEPROM,...).
 */

#ifndef __DEV_C3745_H__
#define __DEV_C3745_H__

#include <pthread.h>

#include "utils.h"
#include "net.h"
#include "device.h"
#include "pci_dev.h"
#include "nmc93cX6.h"
#include "dev_gt.h"
#include "net_io.h"
#include "vm.h"

/* Default C3745 parameters */
#define C3745_DEFAULT_RAM_SIZE     128
#define C3745_DEFAULT_ROM_SIZE     2
#define C3745_DEFAULT_NVRAM_SIZE   128
#define C3745_DEFAULT_CONF_REG     0x2102
#define C3745_DEFAULT_CLOCK_DIV    8
#define C3745_DEFAULT_RAM_MMAP     1
#define C3745_DEFAULT_DISK0_SIZE   16
#define C3745_DEFAULT_DISK1_SIZE   0
#define C3745_DEFAULT_IOMEM_SIZE   5   /* Percents! */

/* 3745 characteritics: 4 NM (+ motherboard), 3 WIC, 2 AIM */
#define C3745_MAX_NM_BAYS   5
#define C3745_MAX_WIC_BAYS  3

/* C3745 DUART Interrupt */
#define C3745_DUART_IRQ  5

/* C3745 Network I/O Interrupt */
#define C3745_NETIO_IRQ  2

/* C3745 GT64k DMA/Timer Interrupt */
#define C3745_GT96K_IRQ  3

/* C3745 External Interrupt */
#define C3745_EXT_IRQ    6

/* Network IRQ */
#define C3745_NETIO_IRQ_BASE       32
#define C3745_NETIO_IRQ_PORT_BITS  2
#define C3745_NETIO_IRQ_PORT_MASK  ((1 << C3745_NETIO_IRQ_PORT_BITS) - 1)
#define C3745_NETIO_IRQ_PER_SLOT   (1 << C3745_NETIO_IRQ_PORT_BITS)
#define C3745_NETIO_IRQ_END        \
  (C3745_NETIO_IRQ_BASE + (C3745_MAX_NM_BAYS * C3745_NETIO_IRQ_PER_SLOT) - 1)

/* C3745 common device addresses */
#define C3745_BITBUCKET_ADDR  0x1ec00000ULL
#define C3745_IOFPGA_ADDR     0x1fa00000ULL
#define C3745_ROM_ADDR        0x1fc00000ULL
#define C3745_GT96K_ADDR      0x24000000ULL
#define C3745_SLOT0_ADDR      0x30000000ULL
#define C3745_SLOT1_ADDR      0x32000000ULL
#define C3745_DUART_ADDR      0x3c100000ULL
#define C3745_WIC_ADDR        0x3c200000ULL
#define C3745_BSWAP_ADDR      0xc0000000ULL
#define C3745_PCI_IO_ADDR     0x100000000ULL

/* WIC interval in address space */
#define C3745_WIC_SIZE  0x2000

/* Offset of simulated NVRAM in ROM flash */
#define C3745_NVRAM_OFFSET    0xB0000
#define C3745_NVRAM_SIZE      0x20000

/* Reserved space for ROM in NVRAM */
#define C3745_NVRAM_ROM_RES_SIZE  2048

/* C3745 ELF Platform ID */
#define C3745_ELF_MACHINE_ID  0x69

#define VM_C3745(vm) ((c3745_t *)vm->hw_data)

/* C3745 router */
typedef struct c3745_router c3745_t;

/* C3745 router */
struct c3745_router {
   /* Chassis MAC address */
   n_eth_addr_t mac_addr;

   /* Associated VM instance */
   vm_instance_t *vm;

   /* GT96100 data */
   struct gt_data *gt_data;

   /* I/O FPGA */
   struct c3745_iofpga_data *iofpga_data;

   /* OIR status */
   m_uint8_t oir_status;

   /* 
    * System EEPROMs.
    * It can be modified to change the chassis MAC address.
    */
   struct cisco_eeprom sys_eeprom[3];
   struct nmc93cX6_group sys_eeprom_group;

   /* Network Module EEPROMs */
   struct nmc93cX6_group nm_eeprom_group[4];
};

/* Get WIC device address for the specified onboard port */
int c3745_get_onboard_wic_addr(u_int slot,m_uint64_t *phys_addr);

/* Set EEPROM for the specified slot */
int c3745_set_slot_eeprom(c3745_t *router,u_int slot,
                          struct cisco_eeprom *eeprom);

/* Get network IRQ for specified slot/port */
u_int c3745_net_irq_for_slot_port(u_int slot,u_int port);

/* Set chassis MAC address */
int c3745_chassis_set_mac_addr(c3745_t *router,char *mac_addr);

/* Show C3745 hardware info */
void c3745_show_hardware(c3745_t *router);

/* Initialize EEPROM groups */
void c3745_init_eeprom_groups(c3745_t *router);

/* dev_c3745_iofpga_init() */
int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len);

/* Register the c3745 platform */
int c3745_platform_register(void);

/* Hypervisor C3745 initialization */
extern int hypervisor_c3745_init(vm_platform_t *platform);

/* NM drivers */
extern struct cisco_card_driver dev_c3745_nm_1fe_tx_driver;
extern struct cisco_card_driver dev_c3745_gt96100_fe_driver;
extern struct cisco_card_driver dev_c3745_nm_4t_driver;
extern struct cisco_card_driver dev_c3745_nm_16esw_driver;
extern struct cisco_card_driver dev_c3745_nm_nam_driver;
extern struct cisco_card_driver dev_c3745_nm_cids_driver;

/* WIC drivers */
extern struct cisco_card_driver *dev_c3745_mb_wic_drivers[];

#endif
1	dpavlin	4	/*
2			* Cisco 3745 simulation platform.
3			* Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4			*
5			* Generic Cisco 3745 routines and definitions (EEPROM,...).
6			*/
7
8			#ifndef __DEV_C3745_H__
9			#define __DEV_C3745_H__
10
11			#include <pthread.h>
12
13			#include "utils.h"
14			#include "net.h"
15			#include "device.h"
16			#include "pci_dev.h"
17	dpavlin	8	#include "nmc93cX6.h"
18	dpavlin	11	#include "dev_gt.h"
19	dpavlin	4	#include "net_io.h"
20			#include "vm.h"
21
22			/* Default C3745 parameters */
23			#define C3745_DEFAULT_RAM_SIZE 128
24			#define C3745_DEFAULT_ROM_SIZE 2
25			#define C3745_DEFAULT_NVRAM_SIZE 128
26			#define C3745_DEFAULT_CONF_REG 0x2102
27			#define C3745_DEFAULT_CLOCK_DIV 8
28			#define C3745_DEFAULT_RAM_MMAP 1
29			#define C3745_DEFAULT_DISK0_SIZE 16
30			#define C3745_DEFAULT_DISK1_SIZE 0
31			#define C3745_DEFAULT_IOMEM_SIZE 5 /* Percents! */
32
33	dpavlin	11	/* 3745 characteritics: 4 NM (+ motherboard), 3 WIC, 2 AIM */
34			#define C3745_MAX_NM_BAYS 5
35			#define C3745_MAX_WIC_BAYS 3
36	dpavlin	4
37			/* C3745 DUART Interrupt */
38			#define C3745_DUART_IRQ 5
39
40			/* C3745 Network I/O Interrupt */
41			#define C3745_NETIO_IRQ 2
42
43			/* C3745 GT64k DMA/Timer Interrupt */
44			#define C3745_GT96K_IRQ 3
45
46			/* C3745 External Interrupt */
47			#define C3745_EXT_IRQ 6
48
49	dpavlin	8	/* Network IRQ */
50			#define C3745_NETIO_IRQ_BASE 32
51			#define C3745_NETIO_IRQ_PORT_BITS 2
52			#define C3745_NETIO_IRQ_PORT_MASK ((1 << C3745_NETIO_IRQ_PORT_BITS) - 1)
53			#define C3745_NETIO_IRQ_PER_SLOT (1 << C3745_NETIO_IRQ_PORT_BITS)
54			#define C3745_NETIO_IRQ_END \
55	dpavlin	11	(C3745_NETIO_IRQ_BASE + (C3745_MAX_NM_BAYS * C3745_NETIO_IRQ_PER_SLOT) - 1)
56	dpavlin	8
57	dpavlin	4	/* C3745 common device addresses */
58	dpavlin	11	#define C3745_BITBUCKET_ADDR 0x1ec00000ULL
59	dpavlin	4	#define C3745_IOFPGA_ADDR 0x1fa00000ULL
60			#define C3745_ROM_ADDR 0x1fc00000ULL
61	dpavlin	11	#define C3745_GT96K_ADDR 0x24000000ULL
62	dpavlin	4	#define C3745_SLOT0_ADDR 0x30000000ULL
63			#define C3745_SLOT1_ADDR 0x32000000ULL
64	dpavlin	11	#define C3745_DUART_ADDR 0x3c100000ULL
65			#define C3745_WIC_ADDR 0x3c200000ULL
66			#define C3745_BSWAP_ADDR 0xc0000000ULL
67	dpavlin	4	#define C3745_PCI_IO_ADDR 0x100000000ULL
68
69	dpavlin	11	/* WIC interval in address space */
70			#define C3745_WIC_SIZE 0x2000
71
72	dpavlin	4	/* Offset of simulated NVRAM in ROM flash */
73			#define C3745_NVRAM_OFFSET 0xB0000
74			#define C3745_NVRAM_SIZE 0x20000
75
76			/* Reserved space for ROM in NVRAM */
77			#define C3745_NVRAM_ROM_RES_SIZE 2048
78
79			/* C3745 ELF Platform ID */
80	dpavlin	11	#define C3745_ELF_MACHINE_ID 0x69
81	dpavlin	4
82	dpavlin	11	#define VM_C3745(vm) ((c3745_t *)vm->hw_data)
83
84	dpavlin	4	/* C3745 router */
85			typedef struct c3745_router c3745_t;
86
87			/* C3745 router */
88			struct c3745_router {
89			/* Chassis MAC address */
90			n_eth_addr_t mac_addr;
91
92			/* Associated VM instance */
93			vm_instance_t *vm;
94
95	dpavlin	11	/* GT96100 data */
96			struct gt_data *gt_data;
97	dpavlin	4
98	dpavlin	8	/* I/O FPGA */
99			struct c3745_iofpga_data *iofpga_data;
100
101	dpavlin	11	/* OIR status */
102	dpavlin	4	m_uint8_t oir_status;
103
104			/*
105			* System EEPROMs.
106			* It can be modified to change the chassis MAC address.
107			*/
108			struct cisco_eeprom sys_eeprom[3];
109	dpavlin	8	struct nmc93cX6_group sys_eeprom_group;
110	dpavlin	4
111			/* Network Module EEPROMs */
112	dpavlin	8	struct nmc93cX6_group nm_eeprom_group[4];
113	dpavlin	4	};
114
115	dpavlin	11	/* Get WIC device address for the specified onboard port */
116			int c3745_get_onboard_wic_addr(u_int slot,m_uint64_t *phys_addr);
117	dpavlin	4
118	dpavlin	11	/* Set EEPROM for the specified slot */
119			int c3745_set_slot_eeprom(c3745_t *router,u_int slot,
120			struct cisco_eeprom *eeprom);
121	dpavlin	4
122	dpavlin	8	/* Get network IRQ for specified slot/port */
123			u_int c3745_net_irq_for_slot_port(u_int slot,u_int port);
124
125	dpavlin	4	/* Set chassis MAC address */
126			int c3745_chassis_set_mac_addr(c3745_t router,char mac_addr);
127
128			/* Show C3745 hardware info */
129			void c3745_show_hardware(c3745_t *router);
130
131			/* Initialize EEPROM groups */
132			void c3745_init_eeprom_groups(c3745_t *router);
133
134			/* dev_c3745_iofpga_init() */
135			int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len);
136
137	dpavlin	11	/* Register the c3745 platform */
138			int c3745_platform_register(void);
139
140			/* Hypervisor C3745 initialization */
141			extern int hypervisor_c3745_init(vm_platform_t *platform);
142
143	dpavlin	4	/* NM drivers */
144	dpavlin	11	extern struct cisco_card_driver dev_c3745_nm_1fe_tx_driver;
145			extern struct cisco_card_driver dev_c3745_gt96100_fe_driver;
146			extern struct cisco_card_driver dev_c3745_nm_4t_driver;
147			extern struct cisco_card_driver dev_c3745_nm_16esw_driver;
148			extern struct cisco_card_driver dev_c3745_nm_nam_driver;
149			extern struct cisco_card_driver dev_c3745_nm_cids_driver;
150	dpavlin	4
151	dpavlin	11	/* WIC drivers */
152			extern struct cisco_card_driver *dev_c3745_mb_wic_drivers[];
153
154	dpavlin	4	#endif