/[dynamips]/trunk/dev_c3600_iofpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/dev_c3600_iofpga.c

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

upstream/dynamips-0.2.6-RC5/dev_c3600_iofpga.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c3600_iofpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 15  Line 15 
15  #include <pthread.h>  #include <pthread.h>
16    
17  #include "ptask.h"  #include "ptask.h"
18  #include "mips64.h"  #include "cpu.h"
19    #include "vm.h"
20  #include "dynamips.h"  #include "dynamips.h"
21  #include "memory.h"  #include "memory.h"
22  #include "device.h"  #include "device.h"
# Line 150  static u_int nm_get_status_2(struct iofp Line 151  static u_int nm_get_status_2(struct iofp
151   * dev_c3620_c3640_iofpga_access()   * dev_c3620_c3640_iofpga_access()
152   */   */
153  static void *  static void *
154  dev_c3620_c3640_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev,  dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
155                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
156                                m_uint64_t *data)                                m_uint64_t *data)
157  {  {
# Line 164  dev_c3620_c3640_iofpga_access(cpu_mips_t Line 165  dev_c3620_c3640_iofpga_access(cpu_mips_t
165     if (offset != 0x0c) {     if (offset != 0x0c) {
166        if (op_type == MTS_READ) {        if (op_type == MTS_READ) {
167           cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",           cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
168                   offset,cpu->pc,op_size);                   offset,cpu_get_pc(cpu),op_size);
169        } else {        } else {
170           cpu_log(cpu,"IO_FPGA",           cpu_log(cpu,"IO_FPGA",
171                   "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                   "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
172                   offset,cpu->pc,*data,op_size);                   offset,cpu_get_pc(cpu),*data,op_size);
173        }        }
174     }     }
175  #endif  #endif
# Line 339  dev_c3620_c3640_iofpga_access(cpu_mips_t Line 340  dev_c3620_c3640_iofpga_access(cpu_mips_t
340           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
341              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
342                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
343                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
344           } else {           } else {
345              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
346                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
347                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
348                        offset,*data,cpu_get_pc(cpu),op_size);
349           }           }
350  #endif  #endif
351     }     }
# Line 355  dev_c3620_c3640_iofpga_access(cpu_mips_t Line 357  dev_c3620_c3640_iofpga_access(cpu_mips_t
357   * dev_c3660_iofpga_access()   * dev_c3660_iofpga_access()
358   */   */
359  static void *  static void *
360  dev_c3660_iofpga_access(cpu_mips_t *cpu,struct vdevice *dev,  dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
361                          m_uint32_t offset,u_int op_size,u_int op_type,                          m_uint32_t offset,u_int op_size,u_int op_type,
362                          m_uint64_t *data)                          m_uint64_t *data)
363  {  {
# Line 369  dev_c3660_iofpga_access(cpu_mips_t *cpu, Line 371  dev_c3660_iofpga_access(cpu_mips_t *cpu,
371     if (offset != 0x0c) {     if (offset != 0x0c) {
372        if (op_type == MTS_READ) {        if (op_type == MTS_READ) {
373           cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",           cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
374                   offset,cpu->pc,op_size);                   offset,cpu_get_pc(cpu),op_size);
375        } else {        } else {
376           cpu_log(cpu,"IO_FPGA",           cpu_log(cpu,"IO_FPGA",
377                   "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                   "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
378                   offset,cpu->pc,*data,op_size);                   offset,cpu_get_pc(cpu),*data,op_size);
379        }        }
380     }     }
381  #endif  #endif
# Line 583  dev_c3660_iofpga_access(cpu_mips_t *cpu, Line 585  dev_c3660_iofpga_access(cpu_mips_t *cpu,
585           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
586              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
587                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
588                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
589           } else {           } else {
590              cpu_log(cpu,"IO_FPGA",              cpu_log(cpu,"IO_FPGA",
591                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
592                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
593                        offset,*data,cpu_get_pc(cpu),op_size);
594           }           }
595  #endif  #endif
596     }     }

Legend:
Removed from v.6  
changed lines
  Added in v.7

  ViewVC Help
Powered by ViewVC 1.1.26