dynamips/trunk/dev_c3600_iofpga.c

/*
 * Cisco router simulation platform.
 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
 *
 * TODO: Online Insertion/Removal (OIR).
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/types.h>
#include <termios.h>
#include <fcntl.h>
#include <pthread.h>

#include "ptask.h"
#include "cpu.h"
#include "vm.h"
#include "dynamips.h"
#include "memory.h"
#include "device.h"
#include "dev_vtty.h"
#include "nmc93cX6.h"
#include "dev_c3600.h"

/* Debugging flags */
#define DEBUG_UNKNOWN   1
#define DEBUG_ACCESS    0
#define DEBUG_NET_IRQ   0

/* Definitions for Mainboard EEPROM */
#define EEPROM_MB_DOUT  3
#define EEPROM_MB_DIN   2
#define EEPROM_MB_CLK   1
#define EEPROM_MB_CS    0

/* Definitions for Network Modules EEPROM */
#define EEPROM_NM_DOUT  7
#define EEPROM_NM_DIN   6
#define EEPROM_NM_CLK   2
#define EEPROM_NM_CS    4

/* Network IRQ distribution */
struct net_irq_distrib  {
   u_int c3620_c3640_offset;
   u_int c3660_reg;
   u_int c3660_offset;
};

/* 
 * Network IRQ distribution for c3620/c3640
 *
 *  Slot 0 | 3620/3640: reg 0x20001 | 3660: reg 0x20010, offset 0
 *  Slot 1 | 3620/3640: reg 0x20000 | 3660: reg 0x10010, offset 24
 *  Slot 2 | 3640     : reg 0x20003 | 3660: reg 0x10010, offset 16
 *  Slot 3 | 3640     : reg 0x20002 | 3660: reg 0x10010, offset 28
 *  Slot 4 | 3620/3640: N/A         | 3660: reg 0x10010, offset 20
 *  Slot 5 | 3620/3640: N/A         | 3660: reg 0x10010, offset 8
 *  Slot 6 | 3620/3640: N/A         | 3660: reg 0x10010, offset 0
 */
static struct net_irq_distrib net_irq_dist[C3600_MAX_NM_BAYS] = {
   { 16, 1, 0  },
   { 24, 0, 24 },
   {  0, 0, 16 },
   {  8, 0, 28 },
   { 32, 0, 20 },
   { 32, 0, 8  },
   { 32, 0, 0  },
};

/* IO FPGA structure */
struct c3600_iofpga_data {
   vm_obj_t vm_obj;
   struct vdevice dev;
   c3600_t *router;
   
   /* Network IRQ status */
   m_uint32_t net_irq_status[2];

   /* Slot select for EEPROM access */
   u_int eeprom_slot;

   /* IO Mask. Don't know the meaning */
   m_uint8_t io_mask;

   m_uint16_t sel;
};

/* Mainboard EEPROM definition */
static const struct nmc93cX6_eeprom_def eeprom_mb_def = {
   EEPROM_MB_CLK, EEPROM_MB_CS,
   EEPROM_MB_DIN, EEPROM_MB_DOUT,
};

/* Mainboard EEPROM */
static const struct nmc93cX6_group eeprom_mb_group = {
   EEPROM_TYPE_NMC93C46, 1, 0, 
   EEPROM_DORD_NORMAL,
   EEPROM_DOUT_HIGH,
   EEPROM_DEBUG_DISABLED,
   "Mainboard EEPROM", 
   { &eeprom_mb_def },
};

/* NM EEPROM definition */
static const struct nmc93cX6_eeprom_def eeprom_nm_def = {
   EEPROM_NM_CLK, EEPROM_NM_CS,
   EEPROM_NM_DIN, EEPROM_NM_DOUT,
};

/* NM EEPROM */
static const struct nmc93cX6_group eeprom_nm_group = {
   EEPROM_TYPE_NMC93C46, 1, 0, 
   EEPROM_DORD_NORMAL,
   EEPROM_DOUT_HIGH,
   EEPROM_DEBUG_DISABLED,
   "NM EEPROM", 
   { &eeprom_nm_def },
};

/* C3660 NM presence masks */
static const m_uint16_t c3660_nm_masks[6] = {
   0xF0FF,   /* slot 1 */
   0xFFF0,   /* slot 2 */
   0x0FFF,   /* slot 3 */
   0xFF0F,   /* slot 4 */
   0xF0FF,   /* slot 5 */
   0xFFF0,   /* slot 6 */
};

/* Select the current NM EEPROM */
static void nm_eeprom_select(struct c3600_iofpga_data *d,u_int slot)
{
   struct cisco_eeprom *eeprom = NULL;
   struct cisco_card *card;

   card = vm_slot_get_card_ptr(d->router->vm,slot);

   if (card != NULL)
      eeprom = &card->eeprom;

   d->router->nm_eeprom_group.eeprom[0] = eeprom;
}

/* Return the NM status register given the detected EEPROM (3620/3640) */
static u_int nm_get_status_1(struct c3600_iofpga_data *d)
{
   u_int res = 0xFFFF;
   int i;

   for(i=0;i<4;i++) {
      if (vm_slot_get_card_ptr(d->router->vm,i))
         res &= ~(0x1111 << i);
   }
   
   return(res);
}

/* Return the NM status register given the detected EEPROM (3660) */
static u_int nm_get_status_2(struct c3600_iofpga_data *d,u_int pos)
{
   u_int res = 0xFFFF;
   u_int start,end;
   int i;

   switch(pos) {
      case 0:  /* word 0: slot 1 - 4 */
         start = 1;
         end   = 4;
         break;
      case 1:  /* word 1: slot 5 - 6 */
         start = 5;
         end = 6;
         break;
      default:
         return(res);
   }

   for(i=start;i<=end;i++) {
      if (vm_slot_get_card_ptr(d->router->vm,i))
         res &= c3660_nm_masks[i-1];
   }
   
   return(res);
}

/* Update network interrupt status */
static inline void 
dev_c3620_c3640_iofpga_net_update_irq(struct c3600_iofpga_data *d)
{
   if (d->net_irq_status[0]) {
      vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
   } else {
      vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
   }
}

static inline void 
dev_c3660_iofpga_net_update_irq(struct c3600_iofpga_data *d)
{
   if (d->net_irq_status[0] || d->net_irq_status[1]) {
      vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
   } else {
      vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
   }
}

/* Trigger a Network IRQ for the specified slot/port */
void dev_c3600_iofpga_net_set_irq(struct c3600_iofpga_data *d,
                                  u_int slot,u_int port)
{
   struct net_irq_distrib *irq_dist;

#if DEBUG_NET_IRQ
   vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n",
          slot,port);
#endif

   irq_dist = &net_irq_dist[slot];

   switch(c3600_chassis_get_id(d->router)) {
      case 3620:
      case 3640:
         d->net_irq_status[0] |= (1 << (irq_dist->c3620_c3640_offset + port));
         dev_c3620_c3640_iofpga_net_update_irq(d);
         break;
      case 3660:
         d->net_irq_status[irq_dist->c3660_reg] |=
            (1 << (irq_dist->c3660_offset + port));
         dev_c3660_iofpga_net_update_irq(d);
         break;
   }
}

/* Clear a Network IRQ for the specified slot/port */
void dev_c3600_iofpga_net_clear_irq(struct c3600_iofpga_data *d,
                                    u_int slot,u_int port)
{
   struct net_irq_distrib *irq_dist;

#if DEBUG_NET_IRQ
   vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n",
          slot,port);
#endif

   irq_dist = &net_irq_dist[slot];

   switch(c3600_chassis_get_id(d->router)) {
      case 3620:
      case 3640:
         d->net_irq_status[0] &= ~(1 << (irq_dist->c3620_c3640_offset + port));
         dev_c3620_c3640_iofpga_net_update_irq(d);
         break;
      case 3660:
         d->net_irq_status[irq_dist->c3660_reg] &=
            ~(1 << (irq_dist->c3660_offset + port));
         dev_c3660_iofpga_net_update_irq(d);
         break;
   }
}

/*
 * dev_c3620_c3640_iofpga_access()
 */
static void *
dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
                              m_uint32_t offset,u_int op_size,u_int op_type,
                              m_uint64_t *data)
{
   struct c3600_iofpga_data *d = dev->priv_data;

   if (op_type == MTS_READ)
      *data = 0x0;

#if DEBUG_ACCESS
   if (offset != 0x0c) {
      if (op_type == MTS_READ) {
         cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
                 offset,cpu_get_pc(cpu),op_size);
      } else {
         cpu_log(cpu,"IO_FPGA",
                 "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
                 offset,cpu_get_pc(cpu),*data,op_size);
      }
   }
#endif

   switch(offset) {
      /* Probably flash protection (if 0, no write access allowed) */
      case 0x00008:
         if (op_type == MTS_READ)
            *data = 0xFF;
         break;

      /* Bootflash of 8 Mb */
      case 0x0000a:
         if (op_type == MTS_READ)
            *data = 0x1000;
         break;

      /* 
       * 0x7d00 is written here regularly.
       * Some kind of hardware watchdog ?
       */     
      case 0x0000c:
         break;

      /* Mainboard EEPROM */
      case 0x0000e:
         if (op_type == MTS_WRITE)
            nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
         else
            *data = nmc93cX6_read(&d->router->mb_eeprom_group);
         break;

      case 0x10004:  /* ??? OIR control ??? */
         if (op_type == MTS_READ) {
            *data = 0x0000;
         }
         break;
         
      /* 
       * Network modules presence.
       *
       * Bit 0: 0 = NM in slot 0 is valid
       * Bit 1: 0 = NM in slot 1 is valid
       * Bit 2: 0 = NM in slot 2 is valid
       * Bit 3: 0 = NM in slot 3 is valid
       *
       * Very well explained on Cisco website:
       * http://www.cisco.com/en/US/customer/products/hw/routers/ps274/products_tech_note09186a0080109510.shtml
       */
      case 0x10006:
         if (op_type == MTS_READ)
            *data = nm_get_status_1(d);
         break;
        
      /*
       * NM EEPROMs.
       */
      case 0x10008:
         if (op_type == MTS_WRITE) {
            d->eeprom_slot = *data & 0x03;
            nm_eeprom_select(d,d->eeprom_slot);
            nmc93cX6_write(&d->router->nm_eeprom_group,*data);
         } else {
            *data = nmc93cX6_read(&d->router->nm_eeprom_group);
         }
         break;

      /* Network interrupt status */
      case 0x20000:   /* slot 1 */
         if (op_type == MTS_READ)
            *data = d->net_irq_status[0] >> 24;
         break;
      case 0x20001:   /* slot 0 */
         if (op_type == MTS_READ)
            *data = d->net_irq_status[0] >> 16;
         break;
      case 0x20002:   /* slot 3 */
         if (op_type == MTS_READ)
            *data = d->net_irq_status[0] >> 8;
         break;
      case 0x20003:   /* slot 2 */
         if (op_type == MTS_READ)
            *data = d->net_irq_status[0];
         break;

      /* 
       * Read when a PA Management interrupt is triggered.
       *
       * If not 0, we get:
       *   "Error: Unexpected NM Interrupt received from slot: x"
       */
      case 0x20004:
         if (op_type == MTS_READ)
            *data = 0x00;
         vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
         break;

      /* 
       * Read when an external interrupt is triggered.
       *
       * Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
       * Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
       *
       * oir_ctrl = register 0x10004
       * oir_stat = register 0x10006
       */
      case 0x20006:
         if (op_type == MTS_READ)
            *data = 0x00;
         vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
         break;

      /* IO Mask (displayed by "show c3600") */
      case 0x20008:
         if (op_type == MTS_READ)
            *data = d->io_mask;
         else
            d->io_mask = *data;
         break;

      /* 
       * Platform type ?
       * 0: 3640, 4 << 5: 3620, 3 << 5: 3660 
       */
      case 0x30000:
         if (op_type == MTS_READ) {
            switch(c3600_chassis_get_id(d->router)) {
               case 3620:
                  *data = 4 << 5;
                  break;
               case 3640:
                  *data = 0 << 5;
                  break;
               case 3660:
                  *data = 3 << 5;
                  break;
               default:
                  *data = 0;
            }
         }
         break;

      /* ??? */
      case 0x30002:
         if (op_type == MTS_WRITE) {
            d->sel = *data;
         } else {
            //*data = d->sel;
         }
         break;

      /* 
       * Environmental parameters, determined with "sh env all". 
       *
       * Bit 0: 0 = overtemperature condition.
       * Bit 4: 0 = RPS present.
       * Bit 5: 0 = Input Voltage status failure.
       * Bit 6: 1 = Thermal status failure.
       * Bit 7: 1 = DC Output Voltage status failure.
       */
      case 0x30004:
         if (op_type == MTS_READ) {
            *data = 32 + 1;
         }
         break;

#if DEBUG_UNKNOWN
      default:
         if (op_type == MTS_READ) {
            cpu_log(cpu,"IO_FPGA",
                    "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
                    offset,cpu_get_pc(cpu),op_size);
         } else {
            cpu_log(cpu,"IO_FPGA",
                    "write to unknown addr 0x%x, value=0x%llx, "
                    "pc=0x%llx (size=%u)\n",
                    offset,*data,cpu_get_pc(cpu),op_size);
         }
#endif
   }

   return NULL;
}

/*
 * dev_c3660_iofpga_access()
 */
static void *
dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
                        m_uint32_t offset,u_int op_size,u_int op_type,
                        m_uint64_t *data)
{
   struct c3600_iofpga_data *d = dev->priv_data;
   u_int slot;

   if (op_type == MTS_READ)
      *data = 0x0;

#if DEBUG_ACCESS
   if (offset != 0x0c) {
      if (op_type == MTS_READ) {
         cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
                 offset,cpu_get_pc(cpu),op_size);
      } else {
         cpu_log(cpu,"IO_FPGA",
                 "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
                 offset,cpu_get_pc(cpu),*data,op_size);
      }
   }
#endif

   switch(offset) {
      /* 
       * 0x7d00 is written here regularly.
       * Some kind of hardware watchdog ?
       */     
      case 0x0000c:
         break;

      /* Probably flash protection (if 0, no write access allowed) */
      case 0x00008:
         if (op_type == MTS_READ)
            *data = 0xFF;
         break;

      /* Bootflash of 8 Mb */
      case 0x0000a:
         if (op_type == MTS_READ)
            *data = 0x1000;
         break;

      /* NM presence - slots 1 to 4 */
      case 0x10006:
         if (op_type == MTS_READ)
            *data = nm_get_status_2(d,0);
         break;

      /* NM presence - slot 5 to 6 */
      case 0x10008:
         if (op_type == MTS_READ)
            *data = nm_get_status_2(d,1);
         break;
      
      /* Fan status, PS presence */
      case 0x10018:
         if (op_type == MTS_READ)
            *data = 0x0000;
         break;

      /* unknown, read by env monitor */
      case 0x1001a: 
         if (op_type == MTS_READ)
            *data = 0x0000;
         break;

      /* board temperature */
      case 0x30004:
         if (op_type == MTS_READ) {
            *data = 32 + 1;
         }
         break;

      /* sh c3600: Per Slot Intr Mask */
      case 0x10016:
         if (op_type == MTS_READ)
            *data = 0x12;
         break;

      /* sh c3600: OIR fsm state slot's (12) */
      case 0x10020:
         if (op_type == MTS_READ)
            *data = 0x00;
         break;

      /* sh c3600: OIR fsm state slot's (34) */
      case 0x10022:
         if (op_type == MTS_READ)
            *data = 0x00;
         break;

      /* sh c3600: OIR fsm state slot's (56) */
      case 0x10024:
         if (op_type == MTS_READ)
            *data = 0x00;
         break;

      /* 
       * Backplane EEPROM.
       *
       * Bit 7: 0=Telco chassis, 1=Enterprise chassis.
       */
      case 0x10000:
         if (op_type == MTS_WRITE)
            nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
         else
            *data = nmc93cX6_read(&d->router->mb_eeprom_group) | 0x80;
         break;

      /* NM EEPROMs - slots 1 to 6 */
      case 0x1000a:
      case 0x1000b:
      case 0x1000c:
      case 0x1000d:
      case 0x1000e:
      case 0x1000f:
         slot = (offset - 0x1000a) + 1;

         if (op_type == MTS_WRITE) {
            nmc93cX6_write(&d->router->c3660_nm_eeprom_group[slot],
                           (u_int)(*data));
         } else {
            *data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[slot]);
         }
         break;

      /* NM EEPROM - slot 0 */
      case 0x20006:
         if (op_type == MTS_WRITE) {
            nmc93cX6_write(&d->router->c3660_nm_eeprom_group[0],
                           (u_int)(*data));
         } else {
            *data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[0]);
         }
         break;

      /* Unknown EEPROMs ? */
      case 0x20000:
      case 0x20002:
      case 0x20004:
         if (op_type == MTS_READ)
            *data = 0xFFFF;
         break;

      /* IO Mask (displayed by "show c3600") */
      case 0x20008:
         if (op_type == MTS_READ)
            *data = d->io_mask;
         else
            d->io_mask = *data;
         break;

      /* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */
      case 0x30000:
         if (op_type == MTS_READ)            
            *data = 3 << 5;
         break;

      /* ??? */   
      case 0x30008:
        if (op_type == MTS_READ)
           *data = 0xFF;
        break;

      /* 
       * Read at net interrupt (size 4).
       * It seems that there are 4 lines per slot.
       *
       *   Bit 24-27: slot 1
       *   Bit 16-19: slot 2
       *   Bit 28-31: slot 3
       *   Bit 20-23: slot 4
       *   Bit 08-11: slot 5
       *   Bit 00-03: slot 6
       *
       * Other bits are unknown.
       */
      case 0x10010:
         if (op_type == MTS_READ)
            *data = d->net_irq_status[0];
         break;

      /* 
       * Read at net interrupt (size 1) 
       *
       *   Bit 7-6: we get "Unexpected AIM interrupt on AIM slot 1".
       *   Bit 5-4: we get "Unexpected AIM interrupt on AIM slot 0".
       *   Bit 0-3: net interrupt for slot 0.
       */        
      case 0x20010:
         if (op_type == MTS_READ)
            *data = d->net_irq_status[1];
         break;

      /* 
       * Read when a PA Management interrupt is triggered.
       *
       * If not 0, we get:
       *   "Error: Unexpected NM Interrupt received from slot: x"
       */
      case 0x10014:
         if (op_type == MTS_READ)
            *data = 0x00;
         vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
         break;

      /* 
       * Read when an external interrupt is triggered.
       *
       * Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
       * Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
       *
       * oir_ctrl = register 0x10004
       * oir_stat = register 0x10006
       */
      case 0x2000a:
         if (op_type == MTS_READ)
            *data = 0x54;
         vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
         break;

#if DEBUG_UNKNOWN
      default:
         if (op_type == MTS_READ) {
            cpu_log(cpu,"IO_FPGA",
                    "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
                    offset,cpu_get_pc(cpu),op_size);
         } else {
            cpu_log(cpu,"IO_FPGA",
                    "write to unknown addr 0x%x, value=0x%llx, "
                    "pc=0x%llx (size=%u)\n",
                    offset,*data,cpu_get_pc(cpu),op_size);
         }
#endif
   }

   return NULL;
}

/* Initialize EEPROM groups */
void c3600_init_eeprom_groups(c3600_t *router)
{
   int i;

   /* Initialize Mainboard EEPROM */
   router->mb_eeprom_group = eeprom_mb_group;
   router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom;
   router->mb_eeprom.data = NULL;
   router->mb_eeprom.len  = 0;

   /* Initialize NM EEPROM for 3620/3640 */
   router->nm_eeprom_group = eeprom_nm_group;
   router->nm_eeprom_group.eeprom[0] = NULL;

   /* Initialize NM EEPROM for 3660 */
   for(i=0;i<C3600_MAX_NM_BAYS;i++) {
      router->c3660_nm_eeprom_group[i] = eeprom_nm_group;
      router->c3660_nm_eeprom_group[i].eeprom[0] = NULL;
   }
}

/* Shutdown the IO FPGA device */
static void 
dev_c3600_iofpga_shutdown(vm_instance_t *vm,struct c3600_iofpga_data *d)
{
   if (d != NULL) {
      /* Remove the device */
      dev_remove(vm,&d->dev);

      /* Free the structure itself */
      free(d);
   }
}

/*
 * dev_c3600_iofpga_init()
 */
int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len)
{
   vm_instance_t *vm = router->vm;
   struct c3600_iofpga_data *d;

   /* Allocate private data structure */
   if (!(d = malloc(sizeof(*d)))) {
      fprintf(stderr,"IO_FPGA: out of memory\n");
      return(-1);
   }

   memset(d,0,sizeof(*d));
   d->router = router;

   vm_object_init(&d->vm_obj);
   d->vm_obj.name = "io_fpga";
   d->vm_obj.data = d;
   d->vm_obj.shutdown = (vm_shutdown_t)dev_c3600_iofpga_shutdown;

   /* Set device properties */
   dev_init(&d->dev);
   d->dev.name      = "io_fpga";
   d->dev.phys_addr = paddr;
   d->dev.phys_len  = len;
   d->dev.priv_data = d;

   switch(router->chassis_driver->chassis_id) {
      case 3620:
      case 3640:
         d->dev.handler = dev_c3620_c3640_iofpga_access;
         break;
      case 3660:
         d->dev.handler = dev_c3660_iofpga_access;
         break;
      default:
         fprintf(stderr,"C3600 '%s': invalid chassis ID %d\n",
                 router->vm->name,router->chassis_driver->chassis_id);
         free(d);
         return(-1);
   }

   /* Map this device to the VM */
   vm_bind_device(router->vm,&d->dev);
   vm_object_add(vm,&d->vm_obj);
   return(0);
}
1	dpavlin	1	/*
2	dpavlin	8	* Cisco router simulation platform.
3	dpavlin	1	* Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4			*
5			* TODO: Online Insertion/Removal (OIR).
6			*/
7
8			#include <stdio.h>
9			#include <stdlib.h>
10			#include <string.h>
11			#include <unistd.h>
12			#include <sys/types.h>
13			#include <termios.h>
14			#include <fcntl.h>
15			#include <pthread.h>
16
17			#include "ptask.h"
18	dpavlin	7	#include "cpu.h"
19			#include "vm.h"
20	dpavlin	1	#include "dynamips.h"
21			#include "memory.h"
22			#include "device.h"
23			#include "dev_vtty.h"
24	dpavlin	8	#include "nmc93cX6.h"
25	dpavlin	1	#include "dev_c3600.h"
26
27			/* Debugging flags */
28			#define DEBUG_UNKNOWN 1
29			#define DEBUG_ACCESS 0
30	dpavlin	8	#define DEBUG_NET_IRQ 0
31	dpavlin	1
32			/* Definitions for Mainboard EEPROM */
33			#define EEPROM_MB_DOUT 3
34			#define EEPROM_MB_DIN 2
35			#define EEPROM_MB_CLK 1
36			#define EEPROM_MB_CS 0
37
38			/* Definitions for Network Modules EEPROM */
39			#define EEPROM_NM_DOUT 7
40			#define EEPROM_NM_DIN 6
41			#define EEPROM_NM_CLK 2
42			#define EEPROM_NM_CS 4
43
44	dpavlin	8	/* Network IRQ distribution */
45			struct net_irq_distrib {
46			u_int c3620_c3640_offset;
47			u_int c3660_reg;
48			u_int c3660_offset;
49			};
50	dpavlin	2
51	dpavlin	8	/*
52			* Network IRQ distribution for c3620/c3640
53			*
54			* Slot 0 \| 3620/3640: reg 0x20001 \| 3660: reg 0x20010, offset 0
55			* Slot 1 \| 3620/3640: reg 0x20000 \| 3660: reg 0x10010, offset 24
56			* Slot 2 \| 3640 : reg 0x20003 \| 3660: reg 0x10010, offset 16
57			* Slot 3 \| 3640 : reg 0x20002 \| 3660: reg 0x10010, offset 28
58			* Slot 4 \| 3620/3640: N/A \| 3660: reg 0x10010, offset 20
59			* Slot 5 \| 3620/3640: N/A \| 3660: reg 0x10010, offset 8
60			* Slot 6 \| 3620/3640: N/A \| 3660: reg 0x10010, offset 0
61			*/
62			static struct net_irq_distrib net_irq_dist[C3600_MAX_NM_BAYS] = {
63			{ 16, 1, 0 },
64			{ 24, 0, 24 },
65			{ 0, 0, 16 },
66			{ 8, 0, 28 },
67			{ 32, 0, 20 },
68			{ 32, 0, 8 },
69			{ 32, 0, 0 },
70			};
71
72	dpavlin	1	/* IO FPGA structure */
73	dpavlin	8	struct c3600_iofpga_data {
74	dpavlin	1	vm_obj_t vm_obj;
75			struct vdevice dev;
76			c3600_t *router;
77	dpavlin	2
78	dpavlin	8	/* Network IRQ status */
79			m_uint32_t net_irq_status[2];
80
81	dpavlin	1	/* Slot select for EEPROM access */
82			u_int eeprom_slot;
83
84			/* IO Mask. Don't know the meaning */
85			m_uint8_t io_mask;
86
87			m_uint16_t sel;
88			};
89
90			/* Mainboard EEPROM definition */
91	dpavlin	8	static const struct nmc93cX6_eeprom_def eeprom_mb_def = {
92	dpavlin	1	EEPROM_MB_CLK, EEPROM_MB_CS,
93			EEPROM_MB_DIN, EEPROM_MB_DOUT,
94			};
95
96			/* Mainboard EEPROM */
97	dpavlin	8	static const struct nmc93cX6_group eeprom_mb_group = {
98	dpavlin	11	EEPROM_TYPE_NMC93C46, 1, 0,
99			EEPROM_DORD_NORMAL,
100			EEPROM_DOUT_HIGH,
101			EEPROM_DEBUG_DISABLED,
102			"Mainboard EEPROM",
103			{ &eeprom_mb_def },
104	dpavlin	1	};
105
106			/* NM EEPROM definition */
107	dpavlin	8	static const struct nmc93cX6_eeprom_def eeprom_nm_def = {
108	dpavlin	1	EEPROM_NM_CLK, EEPROM_NM_CS,
109			EEPROM_NM_DIN, EEPROM_NM_DOUT,
110			};
111
112			/* NM EEPROM */
113	dpavlin	8	static const struct nmc93cX6_group eeprom_nm_group = {
114	dpavlin	11	EEPROM_TYPE_NMC93C46, 1, 0,
115			EEPROM_DORD_NORMAL,
116			EEPROM_DOUT_HIGH,
117			EEPROM_DEBUG_DISABLED,
118			"NM EEPROM",
119			{ &eeprom_nm_def },
120	dpavlin	1	};
121
122			/* C3660 NM presence masks */
123			static const m_uint16_t c3660_nm_masks[6] = {
124			0xF0FF, /* slot 1 */
125			0xFFF0, /* slot 2 */
126			0x0FFF, /* slot 3 */
127			0xFF0F, /* slot 4 */
128			0xF0FF, /* slot 5 */
129			0xFFF0, /* slot 6 */
130			};
131
132			/* Select the current NM EEPROM */
133	dpavlin	8	static void nm_eeprom_select(struct c3600_iofpga_data *d,u_int slot)
134	dpavlin	1	{
135	dpavlin	11	struct cisco_eeprom *eeprom = NULL;
136			struct cisco_card *card;
137
138			card = vm_slot_get_card_ptr(d->router->vm,slot);
139
140			if (card != NULL)
141			eeprom = &card->eeprom;
142
143			d->router->nm_eeprom_group.eeprom[0] = eeprom;
144	dpavlin	1	}
145
146			/* Return the NM status register given the detected EEPROM (3620/3640) */
147	dpavlin	8	static u_int nm_get_status_1(struct c3600_iofpga_data *d)
148	dpavlin	1	{
149			u_int res = 0xFFFF;
150			int i;
151
152			for(i=0;i<4;i++) {
153	dpavlin	11	if (vm_slot_get_card_ptr(d->router->vm,i))
154	dpavlin	1	res &= ~(0x1111 << i);
155			}
156
157			return(res);
158			}
159
160			/* Return the NM status register given the detected EEPROM (3660) */
161	dpavlin	8	static u_int nm_get_status_2(struct c3600_iofpga_data *d,u_int pos)
162	dpavlin	1	{
163			u_int res = 0xFFFF;
164			u_int start,end;
165			int i;
166
167			switch(pos) {
168			case 0: /* word 0: slot 1 - 4 */
169			start = 1;
170			end = 4;
171			break;
172			case 1: /* word 1: slot 5 - 6 */
173			start = 5;
174			end = 6;
175			break;
176			default:
177			return(res);
178			}
179
180			for(i=start;i<=end;i++) {
181	dpavlin	11	if (vm_slot_get_card_ptr(d->router->vm,i))
182	dpavlin	1	res &= c3660_nm_masks[i-1];
183			}
184
185			return(res);
186			}
187
188	dpavlin	8	/* Update network interrupt status */
189			static inline void
190			dev_c3620_c3640_iofpga_net_update_irq(struct c3600_iofpga_data *d)
191			{
192			if (d->net_irq_status[0]) {
193			vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
194			} else {
195			vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
196			}
197			}
198
199			static inline void
200			dev_c3660_iofpga_net_update_irq(struct c3600_iofpga_data *d)
201			{
202			if (d->net_irq_status[0] \|\| d->net_irq_status[1]) {
203			vm_set_irq(d->router->vm,C3600_NETIO_IRQ);
204			} else {
205			vm_clear_irq(d->router->vm,C3600_NETIO_IRQ);
206			}
207			}
208
209			/* Trigger a Network IRQ for the specified slot/port */
210			void dev_c3600_iofpga_net_set_irq(struct c3600_iofpga_data *d,
211			u_int slot,u_int port)
212			{
213			struct net_irq_distrib *irq_dist;
214
215			#if DEBUG_NET_IRQ
216			vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n",
217			slot,port);
218			#endif
219
220			irq_dist = &net_irq_dist[slot];
221
222			switch(c3600_chassis_get_id(d->router)) {
223			case 3620:
224			case 3640:
225			d->net_irq_status[0] \|= (1 << (irq_dist->c3620_c3640_offset + port));
226			dev_c3620_c3640_iofpga_net_update_irq(d);
227			break;
228			case 3660:
229			d->net_irq_status[irq_dist->c3660_reg] \|=
230			(1 << (irq_dist->c3660_offset + port));
231			dev_c3660_iofpga_net_update_irq(d);
232			break;
233			}
234			}
235
236			/* Clear a Network IRQ for the specified slot/port */
237			void dev_c3600_iofpga_net_clear_irq(struct c3600_iofpga_data *d,
238			u_int slot,u_int port)
239			{
240			struct net_irq_distrib *irq_dist;
241
242			#if DEBUG_NET_IRQ
243			vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n",
244			slot,port);
245			#endif
246
247			irq_dist = &net_irq_dist[slot];
248
249			switch(c3600_chassis_get_id(d->router)) {
250			case 3620:
251			case 3640:
252			d->net_irq_status[0] &= ~(1 << (irq_dist->c3620_c3640_offset + port));
253			dev_c3620_c3640_iofpga_net_update_irq(d);
254			break;
255			case 3660:
256			d->net_irq_status[irq_dist->c3660_reg] &=
257			~(1 << (irq_dist->c3660_offset + port));
258			dev_c3660_iofpga_net_update_irq(d);
259			break;
260			}
261			}
262
263	dpavlin	1	/*
264			* dev_c3620_c3640_iofpga_access()
265			*/
266			static void *
267	dpavlin	7	dev_c3620_c3640_iofpga_access(cpu_gen_t cpu,struct vdevice dev,
268	dpavlin	1	m_uint32_t offset,u_int op_size,u_int op_type,
269			m_uint64_t *data)
270			{
271	dpavlin	8	struct c3600_iofpga_data *d = dev->priv_data;
272	dpavlin	1
273			if (op_type == MTS_READ)
274			*data = 0x0;
275
276			#if DEBUG_ACCESS
277			if (offset != 0x0c) {
278			if (op_type == MTS_READ) {
279			cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
280	dpavlin	7	offset,cpu_get_pc(cpu),op_size);
281	dpavlin	1	} else {
282			cpu_log(cpu,"IO_FPGA",
283			"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
284	dpavlin	7	offset,cpu_get_pc(cpu),*data,op_size);
285	dpavlin	1	}
286			}
287			#endif
288
289			switch(offset) {
290			/* Probably flash protection (if 0, no write access allowed) */
291			case 0x00008:
292			if (op_type == MTS_READ)
293			*data = 0xFF;
294			break;
295
296			/* Bootflash of 8 Mb */
297			case 0x0000a:
298			if (op_type == MTS_READ)
299			*data = 0x1000;
300			break;
301
302			/*
303			* 0x7d00 is written here regularly.
304			* Some kind of hardware watchdog ?
305			*/
306			case 0x0000c:
307			break;
308
309			/* Mainboard EEPROM */
310			case 0x0000e:
311			if (op_type == MTS_WRITE)
312	dpavlin	8	nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
313	dpavlin	1	else
314	dpavlin	8	*data = nmc93cX6_read(&d->router->mb_eeprom_group);
315	dpavlin	1	break;
316
317			case 0x10004: /* ??? OIR control ??? */
318			if (op_type == MTS_READ) {
319			*data = 0x0000;
320			}
321			break;
322
323			/*
324			* Network modules presence.
325			*
326			* Bit 0: 0 = NM in slot 0 is valid
327			* Bit 1: 0 = NM in slot 1 is valid
328			* Bit 2: 0 = NM in slot 2 is valid
329			* Bit 3: 0 = NM in slot 3 is valid
330			*
331			* Very well explained on Cisco website:
332			* http://www.cisco.com/en/US/customer/products/hw/routers/ps274/products_tech_note09186a0080109510.shtml
333			*/
334			case 0x10006:
335			if (op_type == MTS_READ)
336			*data = nm_get_status_1(d);
337			break;
338
339			/*
340			* NM EEPROMs.
341			*/
342			case 0x10008:
343			if (op_type == MTS_WRITE) {
344			d->eeprom_slot = *data & 0x03;
345			nm_eeprom_select(d,d->eeprom_slot);
346	dpavlin	8	nmc93cX6_write(&d->router->nm_eeprom_group,*data);
347	dpavlin	1	} else {
348	dpavlin	8	*data = nmc93cX6_read(&d->router->nm_eeprom_group);
349	dpavlin	1	}
350			break;
351
352			/* Network interrupt status */
353	dpavlin	8	case 0x20000: /* slot 1 */
354	dpavlin	1	if (op_type == MTS_READ)
355	dpavlin	8	*data = d->net_irq_status[0] >> 24;
356	dpavlin	1	break;
357	dpavlin	8	case 0x20001: /* slot 0 */
358			if (op_type == MTS_READ)
359			*data = d->net_irq_status[0] >> 16;
360			break;
361			case 0x20002: /* slot 3 */
362			if (op_type == MTS_READ)
363			*data = d->net_irq_status[0] >> 8;
364			break;
365			case 0x20003: /* slot 2 */
366			if (op_type == MTS_READ)
367			*data = d->net_irq_status[0];
368			break;
369	dpavlin	1
370			/*
371			* Read when a PA Management interrupt is triggered.
372			*
373			* If not 0, we get:
374			* "Error: Unexpected NM Interrupt received from slot: x"
375			*/
376			case 0x20004:
377			if (op_type == MTS_READ)
378			*data = 0x00;
379			vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
380			break;
381
382			/*
383			* Read when an external interrupt is triggered.
384			*
385			* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
386			* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
387			*
388			* oir_ctrl = register 0x10004
389			* oir_stat = register 0x10006
390			*/
391			case 0x20006:
392			if (op_type == MTS_READ)
393			*data = 0x00;
394			vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
395			break;
396
397			/* IO Mask (displayed by "show c3600") */
398			case 0x20008:
399			if (op_type == MTS_READ)
400			*data = d->io_mask;
401			else
402			d->io_mask = *data;
403			break;
404
405	dpavlin	5	/*
406			* Platform type ?
407			* 0: 3640, 4 << 5: 3620, 3 << 5: 3660
408			*/
409	dpavlin	1	case 0x30000:
410			if (op_type == MTS_READ) {
411			switch(c3600_chassis_get_id(d->router)) {
412			case 3620:
413			*data = 4 << 5;
414			break;
415			case 3640:
416			*data = 0 << 5;
417			break;
418			case 3660:
419			*data = 3 << 5;
420			break;
421			default:
422			*data = 0;
423			}
424			}
425			break;
426
427			/* ??? */
428			case 0x30002:
429			if (op_type == MTS_WRITE) {
430			d->sel = *data;
431			} else {
432			//*data = d->sel;
433			}
434			break;
435
436			/*
437			* Environmental parameters, determined with "sh env all".
438			*
439			* Bit 0: 0 = overtemperature condition.
440			* Bit 4: 0 = RPS present.
441			* Bit 5: 0 = Input Voltage status failure.
442			* Bit 6: 1 = Thermal status failure.
443			* Bit 7: 1 = DC Output Voltage status failure.
444			*/
445			case 0x30004:
446			if (op_type == MTS_READ) {
447			*data = 32 + 1;
448			}
449			break;
450
451			#if DEBUG_UNKNOWN
452			default:
453			if (op_type == MTS_READ) {
454			cpu_log(cpu,"IO_FPGA",
455			"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
456	dpavlin	7	offset,cpu_get_pc(cpu),op_size);
457	dpavlin	1	} else {
458			cpu_log(cpu,"IO_FPGA",
459			"write to unknown addr 0x%x, value=0x%llx, "
460	dpavlin	7	"pc=0x%llx (size=%u)\n",
461			offset,*data,cpu_get_pc(cpu),op_size);
462	dpavlin	1	}
463			#endif
464			}
465
466			return NULL;
467			}
468
469			/*
470			* dev_c3660_iofpga_access()
471			*/
472			static void *
473	dpavlin	7	dev_c3660_iofpga_access(cpu_gen_t cpu,struct vdevice dev,
474	dpavlin	1	m_uint32_t offset,u_int op_size,u_int op_type,
475			m_uint64_t *data)
476			{
477	dpavlin	8	struct c3600_iofpga_data *d = dev->priv_data;
478	dpavlin	1	u_int slot;
479
480			if (op_type == MTS_READ)
481			*data = 0x0;
482
483			#if DEBUG_ACCESS
484			if (offset != 0x0c) {
485			if (op_type == MTS_READ) {
486			cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
487	dpavlin	7	offset,cpu_get_pc(cpu),op_size);
488	dpavlin	1	} else {
489			cpu_log(cpu,"IO_FPGA",
490			"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
491	dpavlin	7	offset,cpu_get_pc(cpu),*data,op_size);
492	dpavlin	1	}
493			}
494			#endif
495
496			switch(offset) {
497			/*
498			* 0x7d00 is written here regularly.
499			* Some kind of hardware watchdog ?
500			*/
501			case 0x0000c:
502			break;
503
504			/* Probably flash protection (if 0, no write access allowed) */
505			case 0x00008:
506			if (op_type == MTS_READ)
507			*data = 0xFF;
508			break;
509
510			/* Bootflash of 8 Mb */
511			case 0x0000a:
512			if (op_type == MTS_READ)
513			*data = 0x1000;
514			break;
515
516			/* NM presence - slots 1 to 4 */
517			case 0x10006:
518			if (op_type == MTS_READ)
519			*data = nm_get_status_2(d,0);
520			break;
521
522			/* NM presence - slot 5 to 6 */
523			case 0x10008:
524			if (op_type == MTS_READ)
525			*data = nm_get_status_2(d,1);
526			break;
527
528			/* Fan status, PS presence */
529			case 0x10018:
530			if (op_type == MTS_READ)
531			*data = 0x0000;
532			break;
533
534			/* unknown, read by env monitor */
535			case 0x1001a:
536			if (op_type == MTS_READ)
537			*data = 0x0000;
538			break;
539
540			/* board temperature */
541			case 0x30004:
542			if (op_type == MTS_READ) {
543			*data = 32 + 1;
544			}
545			break;
546
547			/* sh c3600: Per Slot Intr Mask */
548			case 0x10016:
549			if (op_type == MTS_READ)
550			*data = 0x12;
551			break;
552
553			/* sh c3600: OIR fsm state slot's (12) */
554			case 0x10020:
555			if (op_type == MTS_READ)
556			*data = 0x00;
557			break;
558
559			/* sh c3600: OIR fsm state slot's (34) */
560			case 0x10022:
561			if (op_type == MTS_READ)
562			*data = 0x00;
563			break;
564
565			/* sh c3600: OIR fsm state slot's (56) */
566			case 0x10024:
567			if (op_type == MTS_READ)
568			*data = 0x00;
569			break;
570
571			/*
572			* Backplane EEPROM.
573			*
574			* Bit 7: 0=Telco chassis, 1=Enterprise chassis.
575			*/
576			case 0x10000:
577			if (op_type == MTS_WRITE)
578	dpavlin	8	nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
579	dpavlin	1	else
580	dpavlin	8	*data = nmc93cX6_read(&d->router->mb_eeprom_group) \| 0x80;
581	dpavlin	1	break;
582
583			/* NM EEPROMs - slots 1 to 6 */
584			case 0x1000a:
585			case 0x1000b:
586			case 0x1000c:
587			case 0x1000d:
588			case 0x1000e:
589			case 0x1000f:
590			slot = (offset - 0x1000a) + 1;
591
592			if (op_type == MTS_WRITE) {
593	dpavlin	8	nmc93cX6_write(&d->router->c3660_nm_eeprom_group[slot],
594	dpavlin	1	(u_int)(*data));
595			} else {
596	dpavlin	8	*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[slot]);
597	dpavlin	1	}
598			break;
599
600			/* NM EEPROM - slot 0 */
601			case 0x20006:
602			if (op_type == MTS_WRITE) {
603	dpavlin	8	nmc93cX6_write(&d->router->c3660_nm_eeprom_group[0],
604	dpavlin	1	(u_int)(*data));
605			} else {
606	dpavlin	8	*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[0]);
607	dpavlin	1	}
608			break;
609
610			/* Unknown EEPROMs ? */
611			case 0x20000:
612			case 0x20002:
613			case 0x20004:
614			if (op_type == MTS_READ)
615			*data = 0xFFFF;
616			break;
617
618			/* IO Mask (displayed by "show c3600") */
619			case 0x20008:
620			if (op_type == MTS_READ)
621			*data = d->io_mask;
622			else
623			d->io_mask = *data;
624			break;
625
626			/* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */
627			case 0x30000:
628			if (op_type == MTS_READ)
629			*data = 3 << 5;
630			break;
631
632			/* ??? */
633			case 0x30008:
634			if (op_type == MTS_READ)
635			*data = 0xFF;
636			break;
637
638			/*
639			* Read at net interrupt (size 4).
640			* It seems that there are 4 lines per slot.
641			*
642			* Bit 24-27: slot 1
643			* Bit 16-19: slot 2
644			* Bit 28-31: slot 3
645			* Bit 20-23: slot 4
646			* Bit 08-11: slot 5
647			* Bit 00-03: slot 6
648			*
649			* Other bits are unknown.
650			*/
651			case 0x10010:
652			if (op_type == MTS_READ)
653	dpavlin	8	*data = d->net_irq_status[0];
654	dpavlin	1	break;
655
656			/*
657			* Read at net interrupt (size 1)
658			*
659			* Bit 7-6: we get "Unexpected AIM interrupt on AIM slot 1".
660			* Bit 5-4: we get "Unexpected AIM interrupt on AIM slot 0".
661			* Bit 0-3: net interrupt for slot 0.
662			*/
663			case 0x20010:
664			if (op_type == MTS_READ)
665	dpavlin	8	*data = d->net_irq_status[1];
666	dpavlin	1	break;
667
668			/*
669			* Read when a PA Management interrupt is triggered.
670			*
671			* If not 0, we get:
672			* "Error: Unexpected NM Interrupt received from slot: x"
673			*/
674			case 0x10014:
675			if (op_type == MTS_READ)
676			*data = 0x00;
677			vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
678			break;
679
680			/*
681			* Read when an external interrupt is triggered.
682			*
683			* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
684			* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
685			*
686			* oir_ctrl = register 0x10004
687			* oir_stat = register 0x10006
688			*/
689			case 0x2000a:
690			if (op_type == MTS_READ)
691			*data = 0x54;
692			vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
693			break;
694
695			#if DEBUG_UNKNOWN
696			default:
697			if (op_type == MTS_READ) {
698			cpu_log(cpu,"IO_FPGA",
699			"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
700	dpavlin	7	offset,cpu_get_pc(cpu),op_size);
701	dpavlin	1	} else {
702			cpu_log(cpu,"IO_FPGA",
703			"write to unknown addr 0x%x, value=0x%llx, "
704	dpavlin	7	"pc=0x%llx (size=%u)\n",
705			offset,*data,cpu_get_pc(cpu),op_size);
706	dpavlin	1	}
707			#endif
708			}
709
710			return NULL;
711			}
712
713			/* Initialize EEPROM groups */
714			void c3600_init_eeprom_groups(c3600_t *router)
715			{
716			int i;
717
718	dpavlin	3	/* Initialize Mainboard EEPROM */
719			router->mb_eeprom_group = eeprom_mb_group;
720			router->mb_eeprom_group.eeprom[0] = &router->mb_eeprom;
721			router->mb_eeprom.data = NULL;
722			router->mb_eeprom.len = 0;
723	dpavlin	1
724	dpavlin	3	/* Initialize NM EEPROM for 3620/3640 */
725			router->nm_eeprom_group = eeprom_nm_group;
726			router->nm_eeprom_group.eeprom[0] = NULL;
727	dpavlin	1
728	dpavlin	3	/* Initialize NM EEPROM for 3660 */
729	dpavlin	1	for(i=0;i<C3600_MAX_NM_BAYS;i++) {
730	dpavlin	3	router->c3660_nm_eeprom_group[i] = eeprom_nm_group;
731	dpavlin	11	router->c3660_nm_eeprom_group[i].eeprom[0] = NULL;
732	dpavlin	1	}
733			}
734
735			/* Shutdown the IO FPGA device */
736	dpavlin	8	static void
737			dev_c3600_iofpga_shutdown(vm_instance_t vm,struct c3600_iofpga_data d)
738	dpavlin	1	{
739			if (d != NULL) {
740			/* Remove the device */
741			dev_remove(vm,&d->dev);
742
743			/* Free the structure itself */
744			free(d);
745			}
746			}
747
748			/*
749			* dev_c3600_iofpga_init()
750			*/
751			int dev_c3600_iofpga_init(c3600_t *router,m_uint64_t paddr,m_uint32_t len)
752			{
753			vm_instance_t *vm = router->vm;
754	dpavlin	8	struct c3600_iofpga_data *d;
755	dpavlin	1
756			/* Allocate private data structure */
757			if (!(d = malloc(sizeof(*d)))) {
758			fprintf(stderr,"IO_FPGA: out of memory\n");
759			return(-1);
760			}
761
762			memset(d,0,sizeof(*d));
763			d->router = router;
764
765			vm_object_init(&d->vm_obj);
766			d->vm_obj.name = "io_fpga";
767			d->vm_obj.data = d;
768			d->vm_obj.shutdown = (vm_shutdown_t)dev_c3600_iofpga_shutdown;
769
770			/* Set device properties */
771			dev_init(&d->dev);
772			d->dev.name = "io_fpga";
773			d->dev.phys_addr = paddr;
774			d->dev.phys_len = len;
775			d->dev.priv_data = d;
776
777			switch(router->chassis_driver->chassis_id) {
778			case 3620:
779			case 3640:
780			d->dev.handler = dev_c3620_c3640_iofpga_access;
781			break;
782			case 3660:
783			d->dev.handler = dev_c3660_iofpga_access;
784			break;
785			default:
786			fprintf(stderr,"C3600 '%s': invalid chassis ID %d\n",
787			router->vm->name,router->chassis_driver->chassis_id);
788			free(d);
789			return(-1);
790			}
791
792			/* Map this device to the VM */
793			vm_bind_device(router->vm,&d->dev);
794			vm_object_add(vm,&d->vm_obj);
795			return(0);
796			}