12 |
#include <sys/types.h> |
#include <sys/types.h> |
13 |
#include <assert.h> |
#include <assert.h> |
14 |
|
|
15 |
#include "mips64.h" |
#include "cpu.h" |
16 |
#include "dynamips.h" |
#include "dynamips.h" |
17 |
#include "memory.h" |
#include "memory.h" |
18 |
#include "device.h" |
#include "device.h" |
19 |
#include "pci_io.h" |
#include "pci_io.h" |
20 |
|
#include "dev_gt.h" |
21 |
#include "cisco_eeprom.h" |
#include "cisco_eeprom.h" |
22 |
|
#include "dev_rom.h" |
23 |
#include "dev_c3600.h" |
#include "dev_c3600.h" |
24 |
|
#include "dev_c3600_iofpga.h" |
25 |
#include "dev_c3600_bay.h" |
#include "dev_c3600_bay.h" |
26 |
#include "dev_vtty.h" |
#include "dev_vtty.h" |
27 |
#include "registry.h" |
#include "registry.h" |
117 |
|
|
118 |
/* Directly extract the configuration from the NVRAM device */ |
/* Directly extract the configuration from the NVRAM device */ |
119 |
ssize_t c3600_nvram_extract_config(vm_instance_t *vm,char **buffer) |
ssize_t c3600_nvram_extract_config(vm_instance_t *vm,char **buffer) |
120 |
{ |
{ |
121 |
struct vdevice *nvram_dev; |
u_char *base_ptr,*ios_ptr,*cfg_ptr,*end_ptr; |
122 |
m_uint32_t start,nvlen; |
m_uint32_t start,nvlen; |
123 |
m_uint16_t magic1,magic2; |
m_uint16_t magic1,magic2; |
124 |
m_uint64_t addr; |
struct vdevice *nvram_dev; |
125 |
|
off_t nvram_size; |
126 |
|
int fd; |
127 |
|
|
128 |
|
if ((nvram_dev = dev_get_by_name(vm,"nvram"))) |
129 |
|
dev_sync(nvram_dev); |
130 |
|
|
131 |
|
fd = vm_mmap_open_file(vm,"nvram",&base_ptr,&nvram_size); |
132 |
|
|
133 |
|
if (fd == -1) |
134 |
|
return(-1); |
135 |
|
|
136 |
if (!(nvram_dev = dev_get_by_name(vm,"nvram"))) |
ios_ptr = base_ptr + vm->nvram_rom_space; |
137 |
|
end_ptr = base_ptr + nvram_size; |
138 |
|
|
139 |
|
if ((ios_ptr + 0x30) >= end_ptr) { |
140 |
|
vm_error(vm,"NVRAM file too small\n"); |
141 |
return(-1); |
return(-1); |
142 |
|
} |
143 |
|
|
144 |
addr = nvram_dev->phys_addr + vm->nvram_rom_space; |
magic1 = ntohs(*PTR_ADJUST(m_uint16_t *,ios_ptr,0x06)); |
145 |
magic1 = physmem_copy_u16_from_vm(vm,addr+0x06); |
magic2 = ntohs(*PTR_ADJUST(m_uint16_t *,ios_ptr,0x08)); |
|
magic2 = physmem_copy_u16_from_vm(vm,addr+0x08); |
|
146 |
|
|
147 |
if ((magic1 != 0xF0A5) || (magic2 != 0xABCD)) { |
if ((magic1 != 0xF0A5) || (magic2 != 0xABCD)) { |
148 |
vm_error(vm,"unable to find IOS magic numbers (0x%x,0x%x)!\n", |
vm_error(vm,"unable to find IOS magic numbers (0x%x,0x%x)!\n", |
150 |
return(-1); |
return(-1); |
151 |
} |
} |
152 |
|
|
153 |
start = physmem_copy_u32_from_vm(vm,addr+0x10) + 1; |
start = ntohl(*PTR_ADJUST(m_uint32_t *,ios_ptr,0x10)) + 1; |
154 |
nvlen = physmem_copy_u32_from_vm(vm,addr+0x18); |
nvlen = ntohl(*PTR_ADJUST(m_uint32_t *,ios_ptr,0x18)); |
155 |
|
|
156 |
if (nvlen <= 10) { |
if (!(*buffer = malloc(nvlen+1))) { |
157 |
vm_error(vm,"invalid configuration size (0x%x)\n",nvlen); |
vm_error(vm,"unable to allocate config buffer (%u bytes)\n",nvlen); |
158 |
return(-1); |
return(-1); |
159 |
} |
} |
160 |
|
|
161 |
if (!(*buffer = malloc(nvlen+1))) { |
cfg_ptr = ios_ptr + start + 0x08; |
162 |
vm_error(vm,"unable to allocate config buffer (%u bytes)\n",nvlen); |
|
163 |
|
if ((cfg_ptr + nvlen) > end_ptr) { |
164 |
|
vm_error(vm,"NVRAM file too small\n"); |
165 |
return(-1); |
return(-1); |
166 |
} |
} |
167 |
|
|
168 |
physmem_copy_from_vm(vm,*buffer,addr+start+0x08,nvlen-1); |
memcpy(*buffer,cfg_ptr,nvlen-1); |
169 |
(*buffer)[nvlen-1] = 0; |
(*buffer)[nvlen-1] = 0; |
170 |
return(nvlen-1); |
return(nvlen-1); |
171 |
} |
} |
173 |
/* Directly push the IOS configuration to the NVRAM device */ |
/* Directly push the IOS configuration to the NVRAM device */ |
174 |
int c3600_nvram_push_config(vm_instance_t *vm,char *buffer,size_t len) |
int c3600_nvram_push_config(vm_instance_t *vm,char *buffer,size_t len) |
175 |
{ |
{ |
176 |
struct vdevice *nvram_dev; |
u_char *base_ptr,*ios_ptr,*cfg_ptr; |
177 |
m_uint64_t addr,cfg_addr; |
m_uint32_t cfg_offset,cklen,tmp; |
|
m_uint32_t tmp,cfg_offset; |
|
|
m_uint32_t cklen; |
|
178 |
m_uint16_t cksum; |
m_uint16_t cksum; |
179 |
|
int fd; |
180 |
|
|
181 |
if (!(nvram_dev = dev_get_by_name(vm,"nvram"))) |
fd = vm_mmap_create_file(vm,"nvram",vm->nvram_size*1024,&base_ptr); |
182 |
|
|
183 |
|
if (fd == -1) |
184 |
return(-1); |
return(-1); |
185 |
|
|
|
addr = nvram_dev->phys_addr + vm->nvram_rom_space; |
|
186 |
cfg_offset = 0x2c; |
cfg_offset = 0x2c; |
187 |
cfg_addr = addr + cfg_offset; |
ios_ptr = base_ptr + vm->nvram_rom_space; |
188 |
|
cfg_ptr = ios_ptr + cfg_offset; |
189 |
|
|
190 |
/* Write IOS tag, uncompressed config... */ |
/* Write IOS tag, uncompressed config... */ |
191 |
physmem_copy_u16_to_vm(vm,addr+0x06,0xF0A5); |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x06) = htons(0xF0A5); |
192 |
physmem_copy_u16_to_vm(vm,addr+0x08,0xABCD); /* Magic number */ |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x08) = htons(0xABCD); |
193 |
physmem_copy_u16_to_vm(vm,addr+0x0a,0x0001); /* ??? */ |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x0a) = htons(0x0001); |
194 |
physmem_copy_u16_to_vm(vm,addr+0x0c,0x0000); /* Checksum */ |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x0c) = htons(0x0000); |
195 |
physmem_copy_u16_to_vm(vm,addr+0x0e,0x0c04); /* IOS version */ |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x0e) = htons(0x0c04); |
196 |
|
|
197 |
/* Store file contents to NVRAM */ |
/* Store file contents to NVRAM */ |
198 |
physmem_copy_to_vm(vm,buffer,cfg_addr,len); |
memcpy(cfg_ptr,buffer,len); |
199 |
|
|
200 |
/* Write config addresses + size */ |
/* Write config addresses + size */ |
201 |
tmp = cfg_addr - addr - 0x08; |
tmp = cfg_offset - 0x08; |
202 |
|
|
203 |
physmem_copy_u32_to_vm(vm,addr+0x10,tmp); |
*PTR_ADJUST(m_uint32_t *,ios_ptr,0x10) = htonl(tmp); |
204 |
physmem_copy_u32_to_vm(vm,addr+0x14,tmp + len); |
*PTR_ADJUST(m_uint32_t *,ios_ptr,0x14) = htonl(tmp + len); |
205 |
physmem_copy_u32_to_vm(vm,addr+0x18,len); |
*PTR_ADJUST(m_uint32_t *,ios_ptr,0x18) = htonl(len); |
206 |
|
|
207 |
/* Compute the checksum */ |
/* Compute the checksum */ |
208 |
cklen = nvram_dev->phys_len - (vm->nvram_rom_space + 0x08); |
cklen = (vm->nvram_size*1024) - (vm->nvram_rom_space + 0x08); |
209 |
cksum = nvram_cksum(vm,addr+0x08,cklen); |
cksum = nvram_cksum((m_uint16_t *)(ios_ptr+0x08),cklen); |
210 |
physmem_copy_u16_to_vm(vm,addr+0x0c,cksum); |
*PTR_ADJUST(m_uint16_t *,ios_ptr,0x0c) = htons(cksum); |
211 |
|
|
212 |
|
vm_mmap_close_file(fd,base_ptr,vm->nvram_size*1024); |
213 |
return(0); |
return(0); |
214 |
} |
} |
215 |
|
|
344 |
registry_foreach_type(OBJ_TYPE_VM,c3600_reg_save_config,fd,NULL); |
registry_foreach_type(OBJ_TYPE_VM,c3600_reg_save_config,fd,NULL); |
345 |
} |
} |
346 |
|
|
347 |
|
/* Get slot/port corresponding to specified network IRQ */ |
348 |
|
static inline void |
349 |
|
c3600_net_irq_get_slot_port(u_int irq,u_int *slot,u_int *port) |
350 |
|
{ |
351 |
|
irq -= C3600_NETIO_IRQ_BASE; |
352 |
|
*port = irq & C3600_NETIO_IRQ_PORT_MASK; |
353 |
|
*slot = irq >> C3600_NETIO_IRQ_PORT_BITS; |
354 |
|
} |
355 |
|
|
356 |
|
/* Get network IRQ for specified slot/port */ |
357 |
|
u_int c3600_net_irq_for_slot_port(u_int slot,u_int port) |
358 |
|
{ |
359 |
|
u_int irq; |
360 |
|
|
361 |
|
irq = (slot << C3600_NETIO_IRQ_PORT_BITS) + port; |
362 |
|
irq += C3600_NETIO_IRQ_BASE; |
363 |
|
|
364 |
|
return(irq); |
365 |
|
} |
366 |
|
|
367 |
/* Set NM EEPROM definition */ |
/* Set NM EEPROM definition */ |
368 |
int c3600_nm_set_eeprom(c3600_t *router,u_int nm_bay, |
int c3600_nm_set_eeprom(c3600_t *router,u_int nm_bay, |
369 |
const struct cisco_eeprom *eeprom) |
const struct cisco_eeprom *eeprom) |
720 |
snprintf(bay->dev_name,len,"%s(%u)",bay->dev_type,nm_bay); |
snprintf(bay->dev_name,len,"%s(%u)",bay->dev_type,nm_bay); |
721 |
|
|
722 |
/* Initialize NM driver */ |
/* Initialize NM driver */ |
723 |
if (bay->nm_driver->nm_init(router,bay->dev_name,nm_bay) == 1) { |
if (bay->nm_driver->nm_init(router,bay->dev_name,nm_bay) == -1) { |
724 |
vm_error(router->vm,"unable to initialize NM %u.\n",nm_bay); |
vm_error(router->vm,"unable to initialize NM %u.\n",nm_bay); |
725 |
return(-1); |
return(-1); |
726 |
} |
} |
1130 |
int i; |
int i; |
1131 |
|
|
1132 |
/* Set the processor type: R4700 */ |
/* Set the processor type: R4700 */ |
1133 |
mips64_set_prid(vm->boot_cpu,MIPS_PRID_R4700); |
mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700); |
1134 |
|
|
1135 |
/* Initialize the Galileo GT-64010 PCI controller */ |
/* Initialize the Galileo GT-64010 PCI controller */ |
1136 |
if (c3600_init_gt64010(router) == -1) |
if (c3600_init_gt64010(router) == -1) |
1152 |
int i; |
int i; |
1153 |
|
|
1154 |
/* Set the processor type: R4700 */ |
/* Set the processor type: R4700 */ |
1155 |
mips64_set_prid(vm->boot_cpu,MIPS_PRID_R4700); |
mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700); |
1156 |
|
|
1157 |
/* Initialize the Galileo GT-64010 PCI controller */ |
/* Initialize the Galileo GT-64010 PCI controller */ |
1158 |
if (c3600_init_gt64010(router) == -1) |
if (c3600_init_gt64010(router) == -1) |
1187 |
int i; |
int i; |
1188 |
|
|
1189 |
/* Set the processor type: R5271 */ |
/* Set the processor type: R5271 */ |
1190 |
mips64_set_prid(vm->boot_cpu,MIPS_PRID_R527x); |
mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x); |
1191 |
|
|
1192 |
/* Initialize the Galileo GT-64120 PCI controller */ |
/* Initialize the Galileo GT-64120 PCI controller */ |
1193 |
if (c3600_init_gt64120(router) == -1) |
if (c3600_init_gt64120(router) == -1) |
1254 |
|
|
1255 |
/* Generate a chassis MAC address based on the instance ID */ |
/* Generate a chassis MAC address based on the instance ID */ |
1256 |
m = &router->mac_addr; |
m = &router->mac_addr; |
1257 |
m->eth_addr_byte[0] = 0xCC; |
m->eth_addr_byte[0] = vm_get_mac_addr_msb(vm); |
1258 |
m->eth_addr_byte[1] = vm->instance_id & 0xFF; |
m->eth_addr_byte[1] = vm->instance_id & 0xFF; |
1259 |
m->eth_addr_byte[2] = pid >> 8; |
m->eth_addr_byte[2] = pid >> 8; |
1260 |
m->eth_addr_byte[3] = pid & 0xFF; |
m->eth_addr_byte[3] = pid & 0xFF; |
1268 |
vm->ram_size = C3600_DEFAULT_RAM_SIZE; |
vm->ram_size = C3600_DEFAULT_RAM_SIZE; |
1269 |
vm->rom_size = C3600_DEFAULT_ROM_SIZE; |
vm->rom_size = C3600_DEFAULT_ROM_SIZE; |
1270 |
vm->nvram_size = C3600_DEFAULT_NVRAM_SIZE; |
vm->nvram_size = C3600_DEFAULT_NVRAM_SIZE; |
1271 |
vm->conf_reg = C3600_DEFAULT_CONF_REG; |
vm->conf_reg_setup = C3600_DEFAULT_CONF_REG; |
1272 |
vm->clock_divisor = C3600_DEFAULT_CLOCK_DIV; |
vm->clock_divisor = C3600_DEFAULT_CLOCK_DIV; |
1273 |
vm->nvram_rom_space = C3600_NVRAM_ROM_RES_SIZE; |
vm->nvram_rom_space = C3600_NVRAM_ROM_RES_SIZE; |
1274 |
router->nm_iomem_size = C3600_DEFAULT_IOMEM_SIZE; |
router->nm_iomem_size = C3600_DEFAULT_IOMEM_SIZE; |
1275 |
|
|
1276 |
vm->pcmcia_disk_size[0] = C3600_DEFAULT_DISK0_SIZE; |
vm->pcmcia_disk_size[0] = C3600_DEFAULT_DISK0_SIZE; |
1277 |
vm->pcmcia_disk_size[1] = C3600_DEFAULT_DISK1_SIZE; |
vm->pcmcia_disk_size[1] = C3600_DEFAULT_DISK1_SIZE; |
1278 |
|
|
1279 |
|
/* Enable NVRAM operations to load/store configs */ |
1280 |
|
vm->nvram_extract_config = c3600_nvram_extract_config; |
1281 |
|
vm->nvram_push_config = c3600_nvram_push_config; |
1282 |
} |
} |
1283 |
|
|
1284 |
/* Initialize the C3600 Platform */ |
/* Initialize the C3600 Platform */ |
1287 |
vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
1288 |
struct c3600_nm_bay *nm_bay; |
struct c3600_nm_bay *nm_bay; |
1289 |
cpu_mips_t *cpu; |
cpu_mips_t *cpu; |
1290 |
|
cpu_gen_t *gen; |
1291 |
|
vm_obj_t *obj; |
1292 |
int i; |
int i; |
1293 |
|
|
1294 |
/* Copy config register setup into "active" config register */ |
/* Copy config register setup into "active" config register */ |
1301 |
vm->cpu_group = cpu_group_create("System CPU"); |
vm->cpu_group = cpu_group_create("System CPU"); |
1302 |
|
|
1303 |
/* Initialize the virtual MIPS processor */ |
/* Initialize the virtual MIPS processor */ |
1304 |
if (!(cpu = cpu_create(vm,0))) { |
if (!(gen = cpu_create(vm,CPU_TYPE_MIPS64,0))) { |
1305 |
vm_error(vm,"unable to create CPU!\n"); |
vm_error(vm,"unable to create CPU!\n"); |
1306 |
return(-1); |
return(-1); |
1307 |
} |
} |
1308 |
|
|
1309 |
|
cpu = CPU_MIPS64(gen); |
1310 |
|
|
1311 |
/* Add this CPU to the system CPU group */ |
/* Add this CPU to the system CPU group */ |
1312 |
cpu_group_add(vm->cpu_group,cpu); |
cpu_group_add(vm->cpu_group,gen); |
1313 |
vm->boot_cpu = cpu; |
vm->boot_cpu = gen; |
1314 |
|
|
1315 |
|
/* Initialize the IRQ routing vectors */ |
1316 |
|
vm->set_irq = mips64_vm_set_irq; |
1317 |
|
vm->clear_irq = mips64_vm_clear_irq; |
1318 |
|
|
1319 |
/* Mark the Network IO interrupt as high priority */ |
/* Mark the Network IO interrupt as high priority */ |
1320 |
cpu->irq_idle_preempt[C3600_NETIO_IRQ] = TRUE; |
cpu->irq_idle_preempt[C3600_NETIO_IRQ] = TRUE; |
1321 |
|
cpu->irq_idle_preempt[C3600_GT64K_IRQ] = TRUE; |
1322 |
cpu->irq_idle_preempt[C3600_DUART_IRQ] = TRUE; |
cpu->irq_idle_preempt[C3600_DUART_IRQ] = TRUE; |
1323 |
|
|
1324 |
/* Copy some parameters from VM to CPU (idle PC, ...) */ |
/* Copy some parameters from VM to CPU (idle PC, ...) */ |
1350 |
if (dev_c3600_iofpga_init(router,C3600_IOFPGA_ADDR,0x40000) == -1) |
if (dev_c3600_iofpga_init(router,C3600_IOFPGA_ADDR,0x40000) == -1) |
1351 |
return(-1); |
return(-1); |
1352 |
|
|
1353 |
|
if (!(obj = vm_object_find(router->vm,"io_fpga"))) |
1354 |
|
return(-1); |
1355 |
|
|
1356 |
|
router->iofpga_data = obj->data; |
1357 |
|
|
1358 |
/* PCI IO space */ |
/* PCI IO space */ |
1359 |
if (!(vm->pci_io_space = pci_io_data_init(vm,C3600_PCI_IO_ADDR))) |
if (!(vm->pci_io_space = pci_io_data_init(vm,C3600_PCI_IO_ADDR))) |
1360 |
return(-1); |
return(-1); |
1364 |
return(-1); |
return(-1); |
1365 |
|
|
1366 |
/* Initialize RAM */ |
/* Initialize RAM */ |
1367 |
dev_ram_init(vm,"ram",vm->ram_mmap,0x00000000ULL,vm->ram_size*1048576); |
vm_ram_init(vm,0x00000000ULL); |
1368 |
|
|
1369 |
/* Initialize ROM */ |
/* Initialize ROM */ |
1370 |
if (!vm->rom_filename) { |
if (!vm->rom_filename) { |
1371 |
/* use embedded ROM */ |
/* use embedded ROM */ |
1372 |
dev_rom_init(vm,"rom",C3600_ROM_ADDR,vm->rom_size*1048576); |
dev_rom_init(vm,"rom",C3600_ROM_ADDR,vm->rom_size*1048576, |
1373 |
|
mips64_microcode,mips64_microcode_len); |
1374 |
} else { |
} else { |
1375 |
/* use alternate ROM */ |
/* use alternate ROM */ |
1376 |
dev_ram_init(vm,"rom",TRUE,C3600_ROM_ADDR,vm->rom_size*1048576); |
dev_ram_init(vm,"rom",TRUE,TRUE,NULL,FALSE, |
1377 |
|
C3600_ROM_ADDR,vm->rom_size*1048576); |
1378 |
} |
} |
1379 |
|
|
1380 |
/* Initialize the NS16552 DUART */ |
/* Initialize the NS16552 DUART */ |
1398 |
} |
} |
1399 |
} |
} |
1400 |
|
|
|
/* Enable NVRAM operations to load/store configs */ |
|
|
vm->nvram_extract_config = c3600_nvram_extract_config; |
|
|
vm->nvram_push_config = c3600_nvram_push_config; |
|
|
|
|
1401 |
/* Show device list */ |
/* Show device list */ |
1402 |
c3600_show_hardware(router); |
c3600_show_hardware(router); |
1403 |
return(0); |
return(0); |
1407 |
int c3600_boot_ios(c3600_t *router) |
int c3600_boot_ios(c3600_t *router) |
1408 |
{ |
{ |
1409 |
vm_instance_t *vm = router->vm; |
vm_instance_t *vm = router->vm; |
1410 |
|
cpu_mips_t *cpu; |
1411 |
|
|
1412 |
if (!vm->boot_cpu) |
if (!vm->boot_cpu) |
1413 |
return(-1); |
return(-1); |
1422 |
} |
} |
1423 |
|
|
1424 |
/* Reset the boot CPU */ |
/* Reset the boot CPU */ |
1425 |
mips64_reset(vm->boot_cpu); |
cpu = CPU_MIPS64(vm->boot_cpu); |
1426 |
|
mips64_reset(cpu); |
1427 |
|
|
1428 |
/* Load IOS image */ |
/* Load IOS image */ |
1429 |
if (mips64_load_elf_image(vm->boot_cpu,vm->ios_image, |
if (mips64_load_elf_image(cpu,vm->ios_image, |
1430 |
|
(vm->ghost_status == VM_GHOST_RAM_USE), |
1431 |
&vm->ios_entry_point) < 0) |
&vm->ios_entry_point) < 0) |
1432 |
{ |
{ |
1433 |
vm_error(vm,"failed to load Cisco IOS image '%s'.\n",vm->ios_image); |
vm_error(vm,"failed to load Cisco IOS image '%s'.\n",vm->ios_image); |
1437 |
/* Launch the simulation */ |
/* Launch the simulation */ |
1438 |
printf("\nC3600 '%s': starting simulation (CPU0 PC=0x%llx), " |
printf("\nC3600 '%s': starting simulation (CPU0 PC=0x%llx), " |
1439 |
"JIT %sabled.\n", |
"JIT %sabled.\n", |
1440 |
vm->name,vm->boot_cpu->pc,vm->jit_use ? "en":"dis"); |
vm->name,cpu->pc,vm->jit_use ? "en":"dis"); |
1441 |
|
|
1442 |
vm_log(vm,"C3600_BOOT", |
vm_log(vm,"C3600_BOOT", |
1443 |
"starting instance (CPU0 PC=0x%llx,idle_pc=0x%llx,JIT %s)\n", |
"starting instance (CPU0 PC=0x%llx,idle_pc=0x%llx,JIT %s)\n", |
1444 |
vm->boot_cpu->pc,vm->boot_cpu->idle_pc,vm->jit_use ? "on":"off"); |
cpu->pc,cpu->idle_pc,vm->jit_use ? "on":"off"); |
1445 |
|
|
1446 |
/* Start main CPU */ |
/* Start main CPU */ |
1447 |
vm->status = VM_STATUS_RUNNING; |
if (vm->ghost_status != VM_GHOST_RAM_GENERATE) { |
1448 |
cpu_start(vm->boot_cpu); |
vm->status = VM_STATUS_RUNNING; |
1449 |
|
cpu_start(vm->boot_cpu); |
1450 |
|
} else { |
1451 |
|
vm->status = VM_STATUS_SHUTDOWN; |
1452 |
|
} |
1453 |
return(0); |
return(0); |
1454 |
} |
} |
1455 |
|
|
1456 |
|
/* Set an IRQ */ |
1457 |
|
static void c3600_set_irq(vm_instance_t *vm,u_int irq) |
1458 |
|
{ |
1459 |
|
c3600_t *router = VM_C3600(vm); |
1460 |
|
cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); |
1461 |
|
u_int slot,port; |
1462 |
|
|
1463 |
|
switch(irq) { |
1464 |
|
case 0 ... 7: |
1465 |
|
mips64_set_irq(cpu0,irq); |
1466 |
|
|
1467 |
|
if (cpu0->irq_idle_preempt[irq]) |
1468 |
|
cpu_idle_break_wait(cpu0->gen); |
1469 |
|
break; |
1470 |
|
|
1471 |
|
case C3600_NETIO_IRQ_BASE ... C3600_NETIO_IRQ_END: |
1472 |
|
c3600_net_irq_get_slot_port(irq,&slot,&port); |
1473 |
|
dev_c3600_iofpga_net_set_irq(router->iofpga_data,slot,port); |
1474 |
|
break; |
1475 |
|
} |
1476 |
|
} |
1477 |
|
|
1478 |
|
/* Clear an IRQ */ |
1479 |
|
static void c3600_clear_irq(vm_instance_t *vm,u_int irq) |
1480 |
|
{ |
1481 |
|
c3600_t *router = VM_C3600(vm); |
1482 |
|
cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); |
1483 |
|
u_int slot,port; |
1484 |
|
|
1485 |
|
switch(irq) { |
1486 |
|
case 0 ... 7: |
1487 |
|
mips64_clear_irq(cpu0,irq); |
1488 |
|
break; |
1489 |
|
|
1490 |
|
case C3600_NETIO_IRQ_BASE ... C3600_NETIO_IRQ_END: |
1491 |
|
c3600_net_irq_get_slot_port(irq,&slot,&port); |
1492 |
|
dev_c3600_iofpga_net_clear_irq(router->iofpga_data,slot,port); |
1493 |
|
break; |
1494 |
|
} |
1495 |
|
} |
1496 |
|
|
1497 |
/* Initialize a Cisco 3600 instance */ |
/* Initialize a Cisco 3600 instance */ |
1498 |
int c3600_init_instance(c3600_t *router) |
int c3600_init_instance(c3600_t *router) |
1499 |
{ |
{ |
1512 |
return(-1); |
return(-1); |
1513 |
} |
} |
1514 |
|
|
1515 |
|
/* IRQ routing */ |
1516 |
|
vm->set_irq = c3600_set_irq; |
1517 |
|
vm->clear_irq = c3600_clear_irq; |
1518 |
|
|
1519 |
/* Load IOS configuration file */ |
/* Load IOS configuration file */ |
1520 |
if (vm->ios_config != NULL) { |
if (vm->ios_config != NULL) { |
1521 |
vm_nvram_push_config(vm,vm->ios_config); |
vm_nvram_push_config(vm,vm->ios_config); |
1523 |
} |
} |
1524 |
|
|
1525 |
/* Load ROM (ELF image or embedded) */ |
/* Load ROM (ELF image or embedded) */ |
1526 |
cpu0 = vm->boot_cpu; |
cpu0 = CPU_MIPS64(vm->boot_cpu); |
1527 |
rom_entry_point = (m_uint32_t)MIPS_ROM_PC; |
rom_entry_point = (m_uint32_t)MIPS_ROM_PC; |
1528 |
|
|
1529 |
if ((vm->rom_filename != NULL) && |
if ((vm->rom_filename != NULL) && |
1530 |
(mips64_load_elf_image(cpu0,vm->rom_filename,&rom_entry_point) < 0)) |
(mips64_load_elf_image(cpu0,vm->rom_filename,0,&rom_entry_point) < 0)) |
1531 |
{ |
{ |
1532 |
vm_error(vm,"unable to load alternate ROM '%s', " |
vm_error(vm,"unable to load alternate ROM '%s', " |
1533 |
"fallback to embedded ROM.\n\n",vm->rom_filename); |
"fallback to embedded ROM.\n\n",vm->rom_filename); |