dynamips/trunk/cpu.h

/*
 * Cisco router simulation platform.
 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
 */

#ifndef __CPU_H__
#define __CPU_H__

#include <pthread.h>
#include "utils.h"
#include "jit_op.h"

#include "mips64.h"
#include "mips64_cp0.h"
#include "ppc32.h"

/* Possible CPU types */
enum {
   CPU_TYPE_MIPS64 = 1,
   CPU_TYPE_PPC32,
};

/* Virtual CPU states */
enum {
   CPU_STATE_RUNNING = 0,
   CPU_STATE_HALTED,
   CPU_STATE_SUSPENDED,
};

/* Maximum results for idle pc */
#define CPU_IDLE_PC_MAX_RES  10

/* Idle PC proposed value */
struct cpu_idle_pc {
   m_uint64_t pc;
   u_int count;
};

/* Number of recorded memory accesses (power of two) */
#define MEMLOG_COUNT   16

typedef struct memlog_access memlog_access_t;
struct memlog_access {
   m_uint64_t iaddr;
   m_uint64_t vaddr;
   m_uint64_t data;
   m_uint32_t data_valid;
   m_uint32_t op_size;
   m_uint32_t op_type;
};

/* Generic CPU definition */
struct cpu_gen {
   /* CPU type and identifier for MP systems */
   u_int type,id;

   /* CPU states */
   volatile u_int state,prev_state;
   volatile m_uint64_t seq_state;

   /* Thread running this CPU */
   pthread_t cpu_thread;
   int cpu_thread_running;

   /* "Idle" loop management */
   u_int idle_count,idle_max,idle_sleep_time;
   pthread_mutex_t idle_mutex;
   pthread_cond_t idle_cond;

   /* VM instance */
   vm_instance_t *vm;

   /* Next CPU in group */
   cpu_gen_t *next;

   /* Idle PC proposal */
   struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES];
   u_int idle_pc_prop_count;

   /* Specific CPU part */
   union {
      cpu_mips_t mips64_cpu;
      cpu_ppc_t ppc32_cpu;
   }sp;

   /* Methods */
   void (*reg_set)(cpu_gen_t *cpu,u_int reg_index,m_uint64_t val);
   void (*reg_dump)(cpu_gen_t *cpu);
   void (*mmu_dump)(cpu_gen_t *cpu);
   void (*mmu_raw_dump)(cpu_gen_t *cpu);
   void (*add_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*remove_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*set_idle_pc)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*get_idling_pc)(cpu_gen_t *cpu);   
   void (*mts_rebuild)(cpu_gen_t *cpu);
   void (*mts_show_stats)(cpu_gen_t *cpu);

   /* Memory access log for fault debugging */
   u_int memlog_pos;
   memlog_access_t memlog_array[MEMLOG_COUNT];

   /* Statistics */
   m_uint64_t dev_access_counter;

   /* JIT op array for current compiled page */
   u_int jit_op_array_size;
   jit_op_t **jit_op_array;
   jit_op_t **jit_op_current;
   
   /* JIT op pool */
   jit_op_t *jit_op_pool[JIT_OP_POOL_NR];
};

/* CPU group definition */
typedef struct cpu_group cpu_group_t;
struct cpu_group {
   char *name;
   cpu_gen_t *cpu_list;
   void *priv_data;
};

#define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu)
#define CPU_PPC32(cpu)  (&(cpu)->sp.ppc32_cpu)

/* Get CPU instruction pointer */
static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu)
{
   switch(cpu->type) {
      case CPU_TYPE_MIPS64:
         return(CPU_MIPS64(cpu)->pc);
      case CPU_TYPE_PPC32:
         return((m_uint64_t)CPU_PPC32(cpu)->ia);
      default:
         return(0);
   }
}

/* Get CPU performance counter */
static forced_inline m_uint64_t cpu_get_perf_counter(cpu_gen_t *cpu)
{
   switch(cpu->type) {
      case CPU_TYPE_MIPS64:
         return(CPU_MIPS64(cpu)->perf_counter);
      case CPU_TYPE_PPC32:
         return(CPU_PPC32(cpu)->perf_counter);
      default:
         return(0);
   }
}

/* Find a CPU in a group given its ID */
cpu_gen_t *cpu_group_find_id(cpu_group_t *group,u_int id);

/* Find the highest CPU ID in a CPU group */
int cpu_group_find_highest_id(cpu_group_t *group,u_int *highest_id);

/* Add a CPU in a CPU group */
int cpu_group_add(cpu_group_t *group,cpu_gen_t *cpu);

/* Create a new CPU group */
cpu_group_t *cpu_group_create(char *name);

/* Delete a CPU group */
void cpu_group_delete(cpu_group_t *group);

/* Rebuild the MTS subsystem for a CPU group */
int cpu_group_rebuild_mts(cpu_group_t *group);

/* Log a message for a CPU */
void cpu_log(cpu_gen_t *cpu,char *module,char *format,...);

/* Create a new CPU */
cpu_gen_t *cpu_create(vm_instance_t *vm,u_int type,u_int id);

/* Delete a CPU */
void cpu_delete(cpu_gen_t *cpu);

/* Start a CPU */
void cpu_start(cpu_gen_t *cpu);

/* Stop a CPU */
void cpu_stop(cpu_gen_t *cpu);

/* Start all CPUs of a CPU group */
void cpu_group_start_all_cpu(cpu_group_t *group);

/* Stop all CPUs of a CPU group */
void cpu_group_stop_all_cpu(cpu_group_t *group);

/* Set a state of all CPUs of a CPU group */
void cpu_group_set_state(cpu_group_t *group,u_int state);

/* Synchronize on CPUs (all CPUs must be inactive) */
int cpu_group_sync_state(cpu_group_t *group);

/* Save state of all CPUs */
int cpu_group_save_state(cpu_group_t *group);

/* Restore state of all CPUs */
int cpu_group_restore_state(cpu_group_t *group);

/* Virtual idle loop */
void cpu_idle_loop(cpu_gen_t *cpu);

/* Break idle wait state */
void cpu_idle_break_wait(cpu_gen_t *cpu);

#endif
1	dpavlin	1	/*
2	dpavlin	7	* Cisco router simulation platform.
3	dpavlin	1	* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4			*/
5
6			#ifndef __CPU_H__
7			#define __CPU_H__
8
9	dpavlin	7	#include <pthread.h>
10			#include "utils.h"
11	dpavlin	9	#include "jit_op.h"
12	dpavlin	7
13	dpavlin	1	#include "mips64.h"
14	dpavlin	7	#include "mips64_cp0.h"
15			#include "ppc32.h"
16	dpavlin	1
17	dpavlin	7	/* Possible CPU types */
18			enum {
19			CPU_TYPE_MIPS64 = 1,
20			CPU_TYPE_PPC32,
21			};
22
23			/* Virtual CPU states */
24			enum {
25			CPU_STATE_RUNNING = 0,
26			CPU_STATE_HALTED,
27			CPU_STATE_SUSPENDED,
28			};
29
30			/* Maximum results for idle pc */
31			#define CPU_IDLE_PC_MAX_RES 10
32
33			/* Idle PC proposed value */
34			struct cpu_idle_pc {
35			m_uint64_t pc;
36			u_int count;
37			};
38
39			/* Number of recorded memory accesses (power of two) */
40			#define MEMLOG_COUNT 16
41
42			typedef struct memlog_access memlog_access_t;
43			struct memlog_access {
44			m_uint64_t iaddr;
45			m_uint64_t vaddr;
46			m_uint64_t data;
47			m_uint32_t data_valid;
48			m_uint32_t op_size;
49			m_uint32_t op_type;
50			};
51
52			/* Generic CPU definition */
53			struct cpu_gen {
54			/* CPU type and identifier for MP systems */
55			u_int type,id;
56
57			/* CPU states */
58			volatile u_int state,prev_state;
59			volatile m_uint64_t seq_state;
60
61			/* Thread running this CPU */
62			pthread_t cpu_thread;
63			int cpu_thread_running;
64
65			/* "Idle" loop management */
66			u_int idle_count,idle_max,idle_sleep_time;
67			pthread_mutex_t idle_mutex;
68			pthread_cond_t idle_cond;
69
70			/* VM instance */
71			vm_instance_t *vm;
72
73			/* Next CPU in group */
74			cpu_gen_t *next;
75
76			/* Idle PC proposal */
77			struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES];
78			u_int idle_pc_prop_count;
79
80			/* Specific CPU part */
81			union {
82			cpu_mips_t mips64_cpu;
83			cpu_ppc_t ppc32_cpu;
84			}sp;
85
86			/* Methods */
87			void (reg_set)(cpu_gen_t cpu,u_int reg_index,m_uint64_t val);
88			void (reg_dump)(cpu_gen_t cpu);
89			void (mmu_dump)(cpu_gen_t cpu);
90			void (mmu_raw_dump)(cpu_gen_t cpu);
91			void (add_breakpoint)(cpu_gen_t cpu,m_uint64_t addr);
92			void (remove_breakpoint)(cpu_gen_t cpu,m_uint64_t addr);
93			void (set_idle_pc)(cpu_gen_t cpu,m_uint64_t addr);
94			void (get_idling_pc)(cpu_gen_t cpu);
95			void (mts_rebuild)(cpu_gen_t cpu);
96			void (mts_show_stats)(cpu_gen_t cpu);
97
98			/* Memory access log for fault debugging */
99			u_int memlog_pos;
100			memlog_access_t memlog_array[MEMLOG_COUNT];
101	dpavlin	8
102			/* Statistics */
103			m_uint64_t dev_access_counter;
104	dpavlin	9
105			/* JIT op array for current compiled page */
106			u_int jit_op_array_size;
107			jit_op_t **jit_op_array;
108			jit_op_t **jit_op_current;
109
110			/* JIT op pool */
111			jit_op_t *jit_op_pool[JIT_OP_POOL_NR];
112	dpavlin	7	};
113
114	dpavlin	1	/* CPU group definition */
115			typedef struct cpu_group cpu_group_t;
116			struct cpu_group {
117			char *name;
118	dpavlin	7	cpu_gen_t *cpu_list;
119	dpavlin	1	void *priv_data;
120			};
121
122	dpavlin	7	#define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu)
123			#define CPU_PPC32(cpu) (&(cpu)->sp.ppc32_cpu)
124
125			/* Get CPU instruction pointer */
126			static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu)
127			{
128			switch(cpu->type) {
129			case CPU_TYPE_MIPS64:
130			return(CPU_MIPS64(cpu)->pc);
131			case CPU_TYPE_PPC32:
132			return((m_uint64_t)CPU_PPC32(cpu)->ia);
133			default:
134			return(0);
135			}
136			}
137
138			/* Get CPU performance counter */
139			static forced_inline m_uint64_t cpu_get_perf_counter(cpu_gen_t *cpu)
140			{
141			switch(cpu->type) {
142			case CPU_TYPE_MIPS64:
143			return(CPU_MIPS64(cpu)->perf_counter);
144			case CPU_TYPE_PPC32:
145			return(CPU_PPC32(cpu)->perf_counter);
146			default:
147			return(0);
148			}
149			}
150
151	dpavlin	1	/* Find a CPU in a group given its ID */
152	dpavlin	7	cpu_gen_t cpu_group_find_id(cpu_group_t group,u_int id);
153	dpavlin	1
154			/* Find the highest CPU ID in a CPU group */
155			int cpu_group_find_highest_id(cpu_group_t group,u_int highest_id);
156
157			/* Add a CPU in a CPU group */
158	dpavlin	7	int cpu_group_add(cpu_group_t group,cpu_gen_t cpu);
159	dpavlin	1
160			/* Create a new CPU group */
161			cpu_group_t cpu_group_create(char name);
162
163			/* Delete a CPU group */
164			void cpu_group_delete(cpu_group_t *group);
165
166			/* Rebuild the MTS subsystem for a CPU group */
167			int cpu_group_rebuild_mts(cpu_group_t *group);
168
169			/* Log a message for a CPU */
170	dpavlin	7	void cpu_log(cpu_gen_t cpu,char module,char *format,...);
171	dpavlin	1
172			/* Create a new CPU */
173	dpavlin	7	cpu_gen_t cpu_create(vm_instance_t vm,u_int type,u_int id);
174	dpavlin	1
175			/* Delete a CPU */
176	dpavlin	7	void cpu_delete(cpu_gen_t *cpu);
177	dpavlin	1
178			/* Start a CPU */
179	dpavlin	7	void cpu_start(cpu_gen_t *cpu);
180	dpavlin	1
181			/* Stop a CPU */
182	dpavlin	7	void cpu_stop(cpu_gen_t *cpu);
183	dpavlin	1
184			/* Start all CPUs of a CPU group */
185			void cpu_group_start_all_cpu(cpu_group_t *group);
186
187			/* Stop all CPUs of a CPU group */
188			void cpu_group_stop_all_cpu(cpu_group_t *group);
189
190			/* Set a state of all CPUs of a CPU group */
191			void cpu_group_set_state(cpu_group_t *group,u_int state);
192
193			/* Synchronize on CPUs (all CPUs must be inactive) */
194			int cpu_group_sync_state(cpu_group_t *group);
195
196			/* Save state of all CPUs */
197			int cpu_group_save_state(cpu_group_t *group);
198
199			/* Restore state of all CPUs */
200			int cpu_group_restore_state(cpu_group_t *group);
201
202	dpavlin	7	/* Virtual idle loop */
203			void cpu_idle_loop(cpu_gen_t *cpu);
204
205			/* Break idle wait state */
206			void cpu_idle_break_wait(cpu_gen_t *cpu);
207
208	dpavlin	1	#endif